riscv/rocket-chip
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jtag: Connect the JTAG DTM side of the synchronizer!

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Megan Wachs 2016-09-26 20:28:26 -07:00 committed by Andrew Waterman
parent 0924f8adb0
commit 449d689a4e
2 changed files with 7 additions and 4 deletions
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6
regression/Makefile
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@ -220,16 +220,16 @@ install_openocd: $(OPENOCD_DIR)/bin/openocd
# Running a list of tests is not supported. # Running a list of tests is not supported.
JTAG_DTM_TEST ?= SimpleRegisterTest.test_s0 JTAG_DTM_TEST ?= SimpleRegisterTest.test_s0
stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp stamps/%/jtag-dtm-32-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \ $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \ --run "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*-debug +vcdplusfile=foo.vpd" \
--cmd="$(OPENOCD_DIR)/bin/openocd \ --cmd="$(OPENOCD_DIR)/bin/openocd \
--s $(OPENOCD_DIR)/share/openocd/scripts" \ --s $(OPENOCD_DIR)/share/openocd/scripts" \
--freedom-e300-sim \ --freedom-e300-sim \
$(JTAG_DTM_TEST) $(JTAG_DTM_TEST)
date > $@ date > $@
stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-ndebug.stamp stamps/%/jtag-dtm-64-$(JTAG_DTM_TEST).stamp: install_openocd stamps/%/vsim-debug.stamp
$(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \ $(abspath $(TOP))/riscv-tools/riscv-tests/debug/gdbserver.py \
--run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \ --run $(abspath $(TOP))/vsim/simv-$(PROJECT)-$* \
--cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd \ --cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd \

5
src/main/scala/rocketchip/DebugTransport.scala
View File

@ -54,7 +54,7 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width)) val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width))
jtag_dtm.io.jtag <> io.jtag jtag_dtm.io.jtag := io.jtag
val dtm_req = Wire(new DecoupledIO(UInt(width = req_width))) val dtm_req = Wire(new DecoupledIO(UInt(width = req_width)))
val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width))) val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width)))
@ -72,6 +72,9 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
dtm_resp.valid := io_debug_bus.resp.valid dtm_resp.valid := io_debug_bus.resp.valid
dtm_resp.bits := io_debug_bus.resp.bits.asUInt dtm_resp.bits := io_debug_bus.resp.bits.asUInt
io_debug_bus.resp.ready := dtm_resp.ready io_debug_bus.resp.ready := dtm_resp.ready
dtm_req := jtag_dtm.io.dtm_req
jtag_dtm.io.dtm_resp := dtm_resp
} }
class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox { class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox {