riscv/rocket-chip
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Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)

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This commit is contained in:
Henry Cook 2014-05-28 14:45:41 -07:00
parent b0ccb88982
commit 434da22283
5 changed files with 9 additions and 8 deletions
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2
chisel

@ -1 +1 @@
Subproject commit 60fb4c60ed0184a5acdaa32535ac417bd691b4c4
Subproject commit 54ad639f11a6ac3459dad4d81e007b3712bd66ba

2
rocket

@ -1 +1 @@
Subproject commit 0a58129f59d70d2650f81a889b79996b81d775ab
Subproject commit fd9bea861cf8cb83ff57c419f8a20964742baba5

9
src/main/scala/RocketChip.scala
View File

@ -201,12 +201,13 @@ class MemDessert extends Module {
class Top extends Module {
val dir = new FullRepresentation(NTILES+1)
val co = if(ENABLE_SHARING) {
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
else new MSICoherence
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence(dir)
else new MSICoherence(dir)
} else {
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
else new MICoherence
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence(dir)
else new MICoherence(dir)
}
implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1)

2
src/main/scala/fpga.scala
View File

@ -74,7 +74,7 @@ class FPGATop extends Module {
val nmshrs = 2
val htif_width = 16
val co = new MESICoherence
val co = new MESICoherence(new FullRepresentation(ntiles+1))
implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1)
implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
implicit val tl = TileLinkConfiguration(co = co, ln = ln,

2
uncore

@ -1 +1 @@
Subproject commit 17cb1806c4688f97342dd001ea2e4c54c2c1153f
Subproject commit ebe0f493a62641a71caec9f2959a4f57e2c16b4e