diff --git a/chisel b/chisel
index 60fb4c60..54ad639f 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit 60fb4c60ed0184a5acdaa32535ac417bd691b4c4
+Subproject commit 54ad639f11a6ac3459dad4d81e007b3712bd66ba
diff --git a/rocket b/rocket
index 0a58129f..fd9bea86 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 0a58129f59d70d2650f81a889b79996b81d775ab
+Subproject commit fd9bea861cf8cb83ff57c419f8a20964742baba5
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 0817c63e..c22a8eb7 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -201,12 +201,13 @@ class MemDessert extends Module {
 
 
 class Top extends Module {
+  val dir = new FullRepresentation(NTILES+1)
   val co = if(ENABLE_SHARING) {
-              if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
-              else new MSICoherence
+              if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence(dir)
+              else new MSICoherence(dir)
             } else {
-              if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
-              else new MICoherence
+              if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence(dir)
+              else new MICoherence(dir)
             }
 
   implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1)
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index 5312a4a3..7f4df49b 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -74,7 +74,7 @@ class FPGATop extends Module {
   val nmshrs = 2
   val htif_width = 16
   
-  val co = new MESICoherence
+  val co = new MESICoherence(new FullRepresentation(ntiles+1))
   implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1)
   implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
   implicit val tl = TileLinkConfiguration(co = co, ln = ln,
diff --git a/uncore b/uncore
index 17cb1806..ebe0f493 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 17cb1806c4688f97342dd001ea2e4c54c2c1153f
+Subproject commit ebe0f493a62641a71caec9f2959a4f57e2c16b4e