riscv/rocket-chip
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Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)

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This commit is contained in:
Henry Cook
2014-05-28 14:45:41 -07:00
parent b0ccb88982
commit 434da22283
5 changed files with 9 additions and 8 deletions
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2
chisel

Submodule chisel updated: 60fb4c60ed...54ad639f11

2
rocket

Submodule rocket updated: 0a58129f59...fd9bea861c

9
src/main/scala/RocketChip.scala
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@ -201,12 +201,13 @@ class MemDessert extends Module {
class Top extends Module { class Top extends Module {
val dir = new FullRepresentation(NTILES+1)
val co = if(ENABLE_SHARING) { val co = if(ENABLE_SHARING) {
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence(dir)
else new MSICoherence else new MSICoherence(dir)
} else { } else {
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence(dir)
else new MICoherence else new MICoherence(dir)
} }
implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1) implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1)

2
src/main/scala/fpga.scala
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@ -74,7 +74,7 @@ class FPGATop extends Module {
val nmshrs = 2 val nmshrs = 2
val htif_width = 16 val htif_width = 16
val co = new MESICoherence val co = new MESICoherence(new FullRepresentation(ntiles+1))
implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1) implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1)
implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS) implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
implicit val tl = TileLinkConfiguration(co = co, ln = ln, implicit val tl = TileLinkConfiguration(co = co, ln = ln,

2
uncore

Submodule uncore updated: 17cb1806c4...ebe0f493a6