riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Bus: remove deprecated crossing attach methods

Browse Source
This commit is contained in:
Wesley W. Terpstra
2017-10-27 01:32:23 -07:00
parent 7cf5d4aa90
commit 41705808dd
2 changed files with 0 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/main/scala/coreplex/SystemBus.scala
View File

@ -70,24 +70,6 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def fromSyncFIFOMaster(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = {
fromSyncPorts(params, name)
}
def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
name.foreach { n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
port_fixer.node :=* sink.node
sink.node
}
def fromAsyncFIFOMaster(depth: Int = 8, sync: Int = 3, name: Option[String] = None): TLAsyncInwardNode = fromAsyncPorts(depth, sync, name)
def fromRationalPorts(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
val sink = LazyModule(new TLRationalCrossingSink(dir))
name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
port_fixer.node :=* sink.node
sink.node
}
def fromRationalFIFOMaster(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = fromRationalPorts(dir, name)
}
/** Provides buses that serve as attachment points,