diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index 138adc81..875a8eb0 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -70,24 +70,6 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   def fromSyncFIFOMaster(params: BufferParams =  BufferParams.default, name: Option[String] = None): TLInwardNode = {
     fromSyncPorts(params, name)
   }
-
-  def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
-    val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
-    name.foreach { n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
-    port_fixer.node :=* sink.node
-    sink.node
-  }
-
-  def fromAsyncFIFOMaster(depth: Int = 8, sync: Int = 3, name: Option[String] = None): TLAsyncInwardNode = fromAsyncPorts(depth, sync, name)
-
-  def fromRationalPorts(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
-    val sink = LazyModule(new TLRationalCrossingSink(dir))
-    name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
-    port_fixer.node :=* sink.node
-    sink.node
-  }
-
-  def fromRationalFIFOMaster(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = fromRationalPorts(dir, name)
 }
 
 /** Provides buses that serve as attachment points,
diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala
index b078358b..31ffba5e 100644
--- a/src/main/scala/tilelink/Bus.scala
+++ b/src/main/scala/tilelink/Bus.scala
@@ -76,50 +76,10 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
     TLBuffer.chain(addBuffers).foldRight(outwardBufNode)(_ :=? _)
   }
 
-  def toAsyncSlaves(sync: Int = 3, name: Option[String] = None, addBuffers: Int = 0): TLAsyncOutwardNode = SinkCardinality { implicit p =>
-    val source = LazyModule(new TLAsyncCrossingSource(sync))
-    name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")}
-    source.node :=? TLBuffer.chain(addBuffers).foldRight(outwardNode)(_ :=? _)
-  }
-
-  def toRationalSlaves(name: Option[String] = None, addBuffers: Int = 0): TLRationalOutwardNode = SinkCardinality { implicit p =>
-    val source = LazyModule(new TLRationalCrossingSource())
-    name.foreach{ n => source.suggestName(s"${busName}_${n}_TLRationalCrossingSource")}
-    source.node :=? TLBuffer.chain(addBuffers).foldRight(outwardNode)(_ :=? _)
-  }
-
   def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
 
-  def toAsyncVariableWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
-    val source = LazyModule(new TLAsyncCrossingSource(sync))
-    name.foreach {n =>  source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
-    source.node :*= outwardFragNode
-    source.node
-  }
-
-  def toRationalVariableWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
-    val source = LazyModule(new TLRationalCrossingSource())
-    name.foreach {n =>  source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
-    source.node :*= outwardFragNode
-    source.node
-  }
-
   def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
 
-  def toAsyncFixedWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
-    val source = LazyModule(new TLAsyncCrossingSource(sync))
-    name.foreach { n => source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
-    source.node := outwardWWNode
-    source.node
-  }
-
-  def toRationalFixedWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
-    val source = LazyModule(new TLRationalCrossingSource())
-    name.foreach {n => source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
-    source.node :*= outwardWWNode
-    source.node
-  }
-
   def toFixedWidthPorts: TLOutwardNode = outwardWWNode // TODO, do/don't buffer here; knowing we will after the necessary port conversions
 
 }