riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

HellaCacheArbiter passes through if n == 1

Browse Source
This commit is contained in:
Howard Mao 2016-07-18 17:01:29 -07:00
parent cff8de9814
commit 40a146f625
1 changed files with 43 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

82
rocket/src/main/scala/arbiter.scala
View File

@ -13,51 +13,55 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
val mem = new HellaCacheIO val mem = new HellaCacheIO
} }
val s1_id = Reg(UInt()) if (n == 1) {
val s2_id = Reg(next=s1_id) io.mem <> io.requestor.head
} else {
val s1_id = Reg(UInt())
val s2_id = Reg(next=s1_id)
io.mem.invalidate_lr := io.requestor.map(_.invalidate_lr).reduce(_||_) io.mem.invalidate_lr := io.requestor.map(_.invalidate_lr).reduce(_||_)
io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_) io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
io.requestor(0).req.ready := io.mem.req.ready io.requestor(0).req.ready := io.mem.req.ready
for (i <- 1 until n) for (i <- 1 until n)
io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid
for (i <- n-1 to 0 by -1) { for (i <- n-1 to 0 by -1) {
val req = io.requestor(i).req val req = io.requestor(i).req
def connect_s0() = { def connect_s0() = {
io.mem.req.bits.cmd := req.bits.cmd io.mem.req.bits.cmd := req.bits.cmd
io.mem.req.bits.typ := req.bits.typ io.mem.req.bits.typ := req.bits.typ
io.mem.req.bits.addr := req.bits.addr io.mem.req.bits.addr := req.bits.addr
io.mem.req.bits.phys := req.bits.phys io.mem.req.bits.phys := req.bits.phys
io.mem.req.bits.tag := Cat(req.bits.tag, UInt(i, log2Up(n))) io.mem.req.bits.tag := Cat(req.bits.tag, UInt(i, log2Up(n)))
s1_id := UInt(i) s1_id := UInt(i)
} }
def connect_s1() = { def connect_s1() = {
io.mem.s1_kill := io.requestor(i).s1_kill io.mem.s1_kill := io.requestor(i).s1_kill
io.mem.s1_data := io.requestor(i).s1_data io.mem.s1_data := io.requestor(i).s1_data
}
if (i == n-1) {
connect_s0()
connect_s1()
} else {
when (req.valid) { connect_s0() }
when (s1_id === UInt(i)) { connect_s1() }
}
} }
if (i == n-1) { for (i <- 0 until n) {
connect_s0() val resp = io.requestor(i).resp
connect_s1() val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UInt(i)
} else { resp.valid := io.mem.resp.valid && tag_hit
when (req.valid) { connect_s0() } io.requestor(i).xcpt := io.mem.xcpt
when (s1_id === UInt(i)) { connect_s1() } io.requestor(i).ordered := io.mem.ordered
io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === UInt(i)
resp.bits := io.mem.resp.bits
resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)
io.requestor(i).replay_next := io.mem.replay_next
} }
} }
for (i <- 0 until n) {
val resp = io.requestor(i).resp
val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UInt(i)
resp.valid := io.mem.resp.valid && tag_hit
io.requestor(i).xcpt := io.mem.xcpt
io.requestor(i).ordered := io.mem.ordered
io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === UInt(i)
resp.bits := io.mem.resp.bits
resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)
io.requestor(i).replay_next := io.mem.replay_next
}
} }
class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int) class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int)