From 40a146f6253a1e707205309d820ad87ab394fab8 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Mon, 18 Jul 2016 17:01:29 -0700
Subject: [PATCH] HellaCacheArbiter passes through if n == 1

---
 rocket/src/main/scala/arbiter.scala | 82 +++++++++++++++--------------
 1 file changed, 43 insertions(+), 39 deletions(-)

diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index 6b3cee53..1a686d5b 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -13,51 +13,55 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
     val mem = new HellaCacheIO
   }
 
-  val s1_id = Reg(UInt())
-  val s2_id = Reg(next=s1_id)
+  if (n == 1) {
+    io.mem <> io.requestor.head
+  } else {
+    val s1_id = Reg(UInt())
+    val s2_id = Reg(next=s1_id)
 
-  io.mem.invalidate_lr := io.requestor.map(_.invalidate_lr).reduce(_||_)
-  io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
-  io.requestor(0).req.ready := io.mem.req.ready
-  for (i <- 1 until n)
-    io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid
+    io.mem.invalidate_lr := io.requestor.map(_.invalidate_lr).reduce(_||_)
+    io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)
+    io.requestor(0).req.ready := io.mem.req.ready
+    for (i <- 1 until n)
+      io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid
 
-  for (i <- n-1 to 0 by -1) {
-    val req = io.requestor(i).req
-    def connect_s0() = {
-      io.mem.req.bits.cmd := req.bits.cmd
-      io.mem.req.bits.typ := req.bits.typ
-      io.mem.req.bits.addr := req.bits.addr
-      io.mem.req.bits.phys := req.bits.phys
-      io.mem.req.bits.tag := Cat(req.bits.tag, UInt(i, log2Up(n)))
-      s1_id := UInt(i)
-    }
-    def connect_s1() = {
-      io.mem.s1_kill := io.requestor(i).s1_kill
-      io.mem.s1_data := io.requestor(i).s1_data
+    for (i <- n-1 to 0 by -1) {
+      val req = io.requestor(i).req
+      def connect_s0() = {
+        io.mem.req.bits.cmd := req.bits.cmd
+        io.mem.req.bits.typ := req.bits.typ
+        io.mem.req.bits.addr := req.bits.addr
+        io.mem.req.bits.phys := req.bits.phys
+        io.mem.req.bits.tag := Cat(req.bits.tag, UInt(i, log2Up(n)))
+        s1_id := UInt(i)
+      }
+      def connect_s1() = {
+        io.mem.s1_kill := io.requestor(i).s1_kill
+        io.mem.s1_data := io.requestor(i).s1_data
+      }
+
+      if (i == n-1) {
+        connect_s0()
+        connect_s1()
+      } else {
+        when (req.valid) { connect_s0() }
+        when (s1_id === UInt(i)) { connect_s1() }
+      }
     }
 
-    if (i == n-1) {
-      connect_s0()
-      connect_s1()
-    } else {
-      when (req.valid) { connect_s0() }
-      when (s1_id === UInt(i)) { connect_s1() }
+    for (i <- 0 until n) {
+      val resp = io.requestor(i).resp
+      val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UInt(i)
+      resp.valid := io.mem.resp.valid && tag_hit
+      io.requestor(i).xcpt := io.mem.xcpt
+      io.requestor(i).ordered := io.mem.ordered
+      io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === UInt(i)
+      resp.bits := io.mem.resp.bits
+      resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)
+
+      io.requestor(i).replay_next := io.mem.replay_next
     }
   }
-
-  for (i <- 0 until n) {
-    val resp = io.requestor(i).resp
-    val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UInt(i)
-    resp.valid := io.mem.resp.valid && tag_hit
-    io.requestor(i).xcpt := io.mem.xcpt
-    io.requestor(i).ordered := io.mem.ordered
-    io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === UInt(i)
-    resp.bits := io.mem.resp.bits
-    resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)
-
-    io.requestor(i).replay_next := io.mem.replay_next
-  }
 }
 
 class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int)