riscv/rocket-chip
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HellaCacheArbiter passes through if n == 1

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This commit is contained in:
Howard Mao 2016-07-18 17:01:29 -07:00
parent cff8de9814
commit 40a146f625
1 changed files with 43 additions and 39 deletions
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4
rocket/src/main/scala/arbiter.scala
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@ -13,6 +13,9 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
val mem = new HellaCacheIO val mem = new HellaCacheIO
} }
if (n == 1) {
io.mem <> io.requestor.head
} else {
val s1_id = Reg(UInt()) val s1_id = Reg(UInt())
val s2_id = Reg(next=s1_id) val s2_id = Reg(next=s1_id)
@ -58,6 +61,7 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
io.requestor(i).replay_next := io.mem.replay_next io.requestor(i).replay_next := io.mem.replay_next
} }
}
} }
class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int) class InOrderArbiter[T <: Data, U <: Data](reqTyp: T, respTyp: U, n: Int)