include fesvr as a library; improve harnesses
This commit is contained in:
Andrew Waterman
parent
f37b9d9a7d
commit
4077b22929
2
chisel
2
chisel
@ -1 +1 @@
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Subproject commit 713523f92973826feaa404044c6b2f6d8bd0e615
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Subproject commit c363ff20e63b20b007738ca8f80930614c2dc6d9
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@ -1,61 +1,53 @@
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#include "htif_phy.h"
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#include <fcntl.h>
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#include <signal.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <map>
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#include "htif_emulator.h"
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#include "common.h"
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#include "emulator.h"
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#include "mm.h"
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#include "mm_dramsim2.h"
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#include "Top.h" // chisel-generated code...
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#include "disasm.h"
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#include "Top.h" // chisel-generated code...
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#include <fcntl.h>
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#include <signal.h>
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#include <stdio.h>
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#include <stdlib.h>
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static bool exit_now = false;
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void handle_sigterm(int signum)
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htif_emulator_t* htif;
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void handle_sigterm(int sig)
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{
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exit_now = true;
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htif->stop();
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}
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int main(int argc, char** argv)
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{
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int fromhost_fd = -1, tohost_fd = -1;
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unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
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uint64_t max_cycles = 0;
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uint64_t trace_count = 0;
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int start = 0;
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bool log = false;
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bool quiet = false;
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const char* vcd = NULL;
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const char* loadmem = NULL;
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FILE *vcdfile = NULL, *logfile = stderr;
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const char* failure = NULL;
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disassembler disasm;
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bool dramsim2 = false;
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signal(SIGTERM, handle_sigterm);
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std::vector<std::string> target_args;
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for (int i = 1; i < argc; i++)
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{
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std::string arg = argv[i];
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if (arg == "-l")
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log = true;
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else if (arg == "-q")
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quiet = true;
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else if (arg == "+dramsim")
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dramsim2 = true;
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else if (arg.substr(0, 2) == "-v")
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if (arg.substr(0, 2) == "-v")
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vcd = argv[i]+2;
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else if (arg.substr(0, 2) == "-m")
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max_cycles = atoll(argv[i]+2);
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else if (arg.substr(0, 2) == "-s")
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random_seed = atoi(argv[i]+2);
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else if (arg.substr(0, 10) == "+fromhost=")
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fromhost_fd = atoi(argv[i]+10);
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else if (arg.substr(0, 8) == "+tohost=")
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tohost_fd = atoi(argv[i]+8);
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else if (arg == "+dramsim")
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dramsim2 = true;
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else if (arg == "+verbose")
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log = true;
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else if (arg.substr(0, 12) == "+max-cycles=")
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max_cycles = atoll(argv[i]+12);
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else if (arg.substr(0, 9) == "+loadmem=")
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loadmem = argv[i]+9;
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else if (arg.substr(0, 1) != "-" || arg.substr(0, 1) != "+")
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target_args = std::vector<std::string>(argv + i, argv + argc);
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else
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{
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fprintf(stderr, "unknown option: %s\n", argv[i]);
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@ -63,8 +55,11 @@ int main(int argc, char** argv)
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}
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}
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demand(fcntl(fromhost_fd,F_GETFD) >= 0, "fromhost file not open");
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demand(fcntl(tohost_fd,F_GETFD) >= 0, "tohost file not open");
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if (target_args.empty())
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{
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fprintf(stderr, "usage: %s [host options] <target program> [target args]\n", argv[0]);
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exit(1);
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}
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const int disasm_len = 24;
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if (vcd)
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@ -89,6 +84,13 @@ int main(int argc, char** argv)
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srand(random_seed);
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tile.init(random_seed != 0);
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// Instantiate HTIF
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htif = new htif_emulator_t(target_args);
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int htif_bits = tile.Top__io_host_in_bits.width();
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assert(htif_bits % 8 == 0 && htif_bits <= val_n_bits());
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signal(SIGTERM, handle_sigterm);
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// reset for a few cycles to support pipelined reset
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tile.Top__io_host_in_valid = LIT<1>(0);
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tile.Top__io_host_out_ready = LIT<1>(0);
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@ -99,9 +101,7 @@ int main(int argc, char** argv)
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tile.clock_hi(LIT<1>(1));
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}
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htif_phy_t htif_phy(tile.Top__io_host_in_bits.width(), fromhost_fd, tohost_fd);
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while (!exit_now)
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while (!htif->done())
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{
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tile.Top__io_mem_req_cmd_ready = LIT<1>(mm->req_cmd_ready());
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tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready());
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@ -109,10 +109,6 @@ int main(int argc, char** argv)
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tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag());
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memcpy(&tile.Top__io_mem_resp_bits_data, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8);
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tile.Top__io_host_in_valid = LIT<1>(htif_phy.in_valid());
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tile.Top__io_host_in_bits = LIT<64>(htif_phy.in_bits());
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tile.Top__io_host_out_ready = LIT<1>(htif_phy.out_ready());
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tile.clock_lo(LIT<1>(0));
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mm->tick(
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@ -127,9 +123,13 @@ int main(int argc, char** argv)
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if (tile.Top__io_host_clk_edge.to_bool())
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{
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htif_phy.tick(tile.Top__io_host_in_ready.lo_word(),
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tile.Top__io_host_out_valid.lo_word(),
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tile.Top__io_host_out_bits.lo_word());
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bool in_valid = tile.Top__io_host_in_ready.to_bool() &&
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htif->recv_nonblocking(&tile.Top__io_host_in_bits.values[0], htif_bits/8);
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tile.Top__io_host_in_valid = LIT<1>(in_valid);
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tile.Top__io_host_out_ready = LIT<1>(1);
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if (tile.Top__io_host_out_valid.to_bool())
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htif->send(&tile.Top__io_host_out_bits.values[0], htif_bits/8);
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}
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@ -152,7 +152,7 @@ int main(int argc, char** argv)
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wb_insn.bits = wb_reg_inst;
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std::string wb_disasm = disasm.disassemble(wb_insn);
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if (log || (quiet && trace_count % 10000 == 0))
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if (log)
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{
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fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
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(long long)trace_count, tile.Top_Tile_core_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_core_dpath__wb_reg_pc.lo_word(), \
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@ -192,8 +192,5 @@ int main(int argc, char** argv)
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return -1;
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}
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close(tohost_fd);
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close(fromhost_fd);
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return 0;
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}
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26
csrc/htif_emulator.h
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26
csrc/htif_emulator.h
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@ -0,0 +1,26 @@
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#ifndef _HTIF_EMULATOR_H
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#define _HTIF_EMULATOR_H
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#include <fesvr/htif_pthread.h>
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class htif_emulator_t : public htif_pthread_t
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{
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public:
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htif_emulator_t(const std::vector<std::string>& args)
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: htif_pthread_t(args)
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{
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}
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void set_clock_divisor(int divisor, int hold_cycles)
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{
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write_cr(-1, 63, divisor | hold_cycles << 16);
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}
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void start()
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{
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set_clock_divisor(5, 2);
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htif_pthread_t::start();
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}
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};
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#endif
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@ -1,10 +1,16 @@
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#include "htif_phy.h"
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#include "htif_emulator.h"
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#include "mm.h"
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#include "mm_dramsim2.h"
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#include <DirectC.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <vector>
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#include <sstream>
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#include <iterator>
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htif_phy_t* htif_phy = NULL;
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mm_t* mm = NULL;
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static htif_emulator_t* htif = NULL;
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static unsigned htif_bytes;
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static mm_t* mm = NULL;
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extern "C" {
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@ -56,9 +62,8 @@ void memory_tick(
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void htif_init
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(
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vc_handle fromhost,
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vc_handle tohost,
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vc_handle width,
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vc_handle argv,
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vc_handle loadmem,
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vc_handle dramsim
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)
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@ -66,17 +71,34 @@ void htif_init
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mm = vc_getScalar(dramsim) ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
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mm->init(MEM_SIZE);
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vec32* fh = vc_4stVectorRef(fromhost);
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vec32* th = vc_4stVectorRef(tohost);
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vec32* w = vc_4stVectorRef(width);
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assert(w->d <= 32 && w->d % 8 == 0); // htif_tick assumes data fits in a vec32
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htif_bytes = w->d/8;
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char loadmem_str[1024];
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vc_VectorToString(loadmem, loadmem_str);
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if (*loadmem_str)
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load_mem(mm->get_data(), loadmem_str);
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assert(w->d <= 32); // htif_tick assumes data fits in a vec32
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htif_phy = new htif_phy_t(w->d, fh->d, th->d);
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char argv_str[1024];
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vc_VectorToString(argv, argv_str);
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if (!*argv_str)
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{
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if (*loadmem_str)
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strcpy(argv_str, "none");
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else
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{
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fprintf(stderr, "Usage: ./simv [host options] +argv=\"<target program> [target args]\"\n");
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exit(-1);
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}
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}
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std::vector<std::string> args;
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std::stringstream ss(argv_str);
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std::istream_iterator<std::string> begin(ss), end;
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std::copy(begin, end, std::back_inserter<std::vector<std::string>>(args));
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htif = new htif_emulator_t(args);
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}
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void htif_tick
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@ -86,19 +108,28 @@ void htif_tick
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vc_handle htif_in_bits,
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vc_handle htif_out_valid,
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vc_handle htif_out_ready,
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vc_handle htif_out_bits
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vc_handle htif_out_bits,
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vc_handle exit
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)
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{
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vec32* ob = vc_4stVectorRef(htif_out_bits);
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htif_phy->tick(vc_getScalar(htif_in_ready), vc_getScalar(htif_out_valid), ob->d);
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static bool peek_in_valid;
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static uint32_t peek_in_bits;
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if (vc_getScalar(htif_in_ready))
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peek_in_valid = htif->recv_nonblocking(&peek_in_bits, htif_bytes);
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vc_putScalar(htif_in_valid, htif_phy->in_valid());
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vc_putScalar(htif_out_ready, htif_phy->out_ready());
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vc_putScalar(htif_out_ready, 1);
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if (vc_getScalar(htif_out_valid))
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{
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vec32* bits = vc_4stVectorRef(htif_out_bits);
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htif->send(&bits->d, htif_bytes);
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}
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vec32 ib;
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ib.c = 0;
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ib.d = htif_phy->in_bits();
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vc_put4stVector(htif_in_bits, &ib);
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vec32 bits = {0, 0};
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bits.d = peek_in_bits;
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vc_put4stVector(htif_in_bits, &bits);
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vc_putScalar(htif_in_valid, peek_in_valid);
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vc_putScalar(exit, htif->done() ? (htif->exit_code() << 1 | 1) : 0);
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}
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}
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@ -4,11 +4,13 @@ basedir = ..
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include ../Makefrag
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CXX := g++
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CXXFLAGS := -O1 -std=c++0x
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CXXFLAGS := $(CXXFLAGS) -O1 -std=c++0x -I$(RISCV)/include
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CXXSRCS := emulator disasm mm mm_dramsim2
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CXXFLAGS := $(CXXFLAGS) -I$(basedir)/csrc -I$(basedir)/chisel/csrc -I$(basedir)/dramsim2
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LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread
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OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
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DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
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@ -34,10 +36,10 @@ $(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(basedir)/csrc/%.cc $(basedir)/csr
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$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
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emulator: $(OBJS) libdramsim.a
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$(CXX) $(CXXFLAGS) -o $@ $(OBJS) -L. -ldramsim
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$(CXX) $(CXXFLAGS) -o $@ $(OBJS) $(LDFLAGS)
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emulator-debug: $(DEBUG_OBJS) libdramsim.a
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$(CXX) $(CXXFLAGS) -o $@ $(DEBUG_OBJS) -L. -ldramsim
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$(CXX) $(CXXFLAGS) -o $@ $(DEBUG_OBJS) $(LDFLAGS)
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clean:
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rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output
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@ -67,13 +69,13 @@ output:
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mkdir -p $@
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output/%.run: output/%.hex emulator
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fesvr +dramsim -c -testrun -m3000000 +loadmem=$< none 2> /dev/null
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./emulator +dramsim +max-cycles=3000000 +loadmem=$< none 2> /dev/null
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output/%.out: output/%.hex emulator
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fesvr +dramsim -c -testrun -m3000000 -l +loadmem=$< none 2> $@
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./emulator +dramsim +max-cycles=3000000 +verbose +loadmem=$< none 2> $@
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output/%.vpd: output/%.hex emulator-debug
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fesvr +dramsim -c./emulator-debug -testrun -m3000000 -l -v- +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@) | vcd2vpd - $@ > /dev/null && [ $$PIPESTATUS -eq 0 ]
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./emulator-debug +dramsim +max-cycles=3000000 +verbose -v- +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@) | vcd2vpd - $@ > /dev/null && [ $$PIPESTATUS -eq 0 ]
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run-asm-tests: $(addprefix output/, $(addsuffix .out, $(global_asm_tests) $(global_asm_vm_tests)))
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@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
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@ -1 +1 @@
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Subproject commit 062076bd5826671871c710ad8ef89b2237626600
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Subproject commit 2a91f23857ce35d59217a295202710be4ec8d5dc
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@ -4,6 +4,7 @@ import Chisel._
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import Node._
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import uncore._
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import rocket._
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import rocket.Util._
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import ReferenceChipBackend._
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import scala.collection.mutable.ArrayBuffer
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import scala.collection.mutable.HashMap
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@ -290,7 +291,11 @@ class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit
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outmemsys.io.mem_backup_en <> io.mem_backup_en
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// pad out the HTIF using a divided clock
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val hio = (new slowIO(8)) { Bits(width = htif_width+1) }
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val hio = (new SlowIO(512)) { Bits(width = htif_width+1) }
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hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
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hio.io.set_divisor.bits := htif.io.scr.wdata
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htif.io.scr.rdata(63) := hio.io.divisor
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hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid
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hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits))
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htif.io.host.out.ready := hio.io.out_fast.ready
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit 7270cf1702656098ffd217d28dac80ddc8c57a60
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Subproject commit 871f7a86bc4540ca51ad397c8d29b6ea2363fd25
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