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include fesvr as a library; improve harnesses

This commit is contained in:
Andrew Waterman 2013-01-24 23:56:45 -08:00
parent f37b9d9a7d
commit 4077b22929
8 changed files with 132 additions and 71 deletions

2
chisel

@ -1 +1 @@
Subproject commit 713523f92973826feaa404044c6b2f6d8bd0e615 Subproject commit c363ff20e63b20b007738ca8f80930614c2dc6d9

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@ -1,61 +1,53 @@
#include "htif_phy.h" #include "htif_emulator.h"
#include <fcntl.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include <map>
#include "common.h" #include "common.h"
#include "emulator.h" #include "emulator.h"
#include "mm.h" #include "mm.h"
#include "mm_dramsim2.h" #include "mm_dramsim2.h"
#include "Top.h" // chisel-generated code...
#include "disasm.h" #include "disasm.h"
#include "Top.h" // chisel-generated code...
#include <fcntl.h>
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
static bool exit_now = false; htif_emulator_t* htif;
void handle_sigterm(int signum) void handle_sigterm(int sig)
{ {
exit_now = true; htif->stop();
} }
int main(int argc, char** argv) int main(int argc, char** argv)
{ {
int fromhost_fd = -1, tohost_fd = -1;
unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid(); unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
uint64_t max_cycles = 0; uint64_t max_cycles = 0;
uint64_t trace_count = 0; uint64_t trace_count = 0;
int start = 0; int start = 0;
bool log = false; bool log = false;
bool quiet = false;
const char* vcd = NULL; const char* vcd = NULL;
const char* loadmem = NULL; const char* loadmem = NULL;
FILE *vcdfile = NULL, *logfile = stderr; FILE *vcdfile = NULL, *logfile = stderr;
const char* failure = NULL; const char* failure = NULL;
disassembler disasm; disassembler disasm;
bool dramsim2 = false; bool dramsim2 = false;
std::vector<std::string> target_args;
signal(SIGTERM, handle_sigterm);
for (int i = 1; i < argc; i++) for (int i = 1; i < argc; i++)
{ {
std::string arg = argv[i]; std::string arg = argv[i];
if (arg == "-l") if (arg.substr(0, 2) == "-v")
log = true;
else if (arg == "-q")
quiet = true;
else if (arg == "+dramsim")
dramsim2 = true;
else if (arg.substr(0, 2) == "-v")
vcd = argv[i]+2; vcd = argv[i]+2;
else if (arg.substr(0, 2) == "-m")
max_cycles = atoll(argv[i]+2);
else if (arg.substr(0, 2) == "-s") else if (arg.substr(0, 2) == "-s")
random_seed = atoi(argv[i]+2); random_seed = atoi(argv[i]+2);
else if (arg.substr(0, 10) == "+fromhost=") else if (arg == "+dramsim")
fromhost_fd = atoi(argv[i]+10); dramsim2 = true;
else if (arg.substr(0, 8) == "+tohost=") else if (arg == "+verbose")
tohost_fd = atoi(argv[i]+8); log = true;
else if (arg.substr(0, 12) == "+max-cycles=")
max_cycles = atoll(argv[i]+12);
else if (arg.substr(0, 9) == "+loadmem=") else if (arg.substr(0, 9) == "+loadmem=")
loadmem = argv[i]+9; loadmem = argv[i]+9;
else if (arg.substr(0, 1) != "-" || arg.substr(0, 1) != "+")
target_args = std::vector<std::string>(argv + i, argv + argc);
else else
{ {
fprintf(stderr, "unknown option: %s\n", argv[i]); fprintf(stderr, "unknown option: %s\n", argv[i]);
@ -63,8 +55,11 @@ int main(int argc, char** argv)
} }
} }
demand(fcntl(fromhost_fd,F_GETFD) >= 0, "fromhost file not open"); if (target_args.empty())
demand(fcntl(tohost_fd,F_GETFD) >= 0, "tohost file not open"); {
fprintf(stderr, "usage: %s [host options] <target program> [target args]\n", argv[0]);
exit(1);
}
const int disasm_len = 24; const int disasm_len = 24;
if (vcd) if (vcd)
@ -89,6 +84,13 @@ int main(int argc, char** argv)
srand(random_seed); srand(random_seed);
tile.init(random_seed != 0); tile.init(random_seed != 0);
// Instantiate HTIF
htif = new htif_emulator_t(target_args);
int htif_bits = tile.Top__io_host_in_bits.width();
assert(htif_bits % 8 == 0 && htif_bits <= val_n_bits());
signal(SIGTERM, handle_sigterm);
// reset for a few cycles to support pipelined reset // reset for a few cycles to support pipelined reset
tile.Top__io_host_in_valid = LIT<1>(0); tile.Top__io_host_in_valid = LIT<1>(0);
tile.Top__io_host_out_ready = LIT<1>(0); tile.Top__io_host_out_ready = LIT<1>(0);
@ -99,9 +101,7 @@ int main(int argc, char** argv)
tile.clock_hi(LIT<1>(1)); tile.clock_hi(LIT<1>(1));
} }
htif_phy_t htif_phy(tile.Top__io_host_in_bits.width(), fromhost_fd, tohost_fd); while (!htif->done())
while (!exit_now)
{ {
tile.Top__io_mem_req_cmd_ready = LIT<1>(mm->req_cmd_ready()); tile.Top__io_mem_req_cmd_ready = LIT<1>(mm->req_cmd_ready());
tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready()); tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready());
@ -109,10 +109,6 @@ int main(int argc, char** argv)
tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag()); tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag());
memcpy(&tile.Top__io_mem_resp_bits_data, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8); memcpy(&tile.Top__io_mem_resp_bits_data, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8);
tile.Top__io_host_in_valid = LIT<1>(htif_phy.in_valid());
tile.Top__io_host_in_bits = LIT<64>(htif_phy.in_bits());
tile.Top__io_host_out_ready = LIT<1>(htif_phy.out_ready());
tile.clock_lo(LIT<1>(0)); tile.clock_lo(LIT<1>(0));
mm->tick( mm->tick(
@ -127,9 +123,13 @@ int main(int argc, char** argv)
if (tile.Top__io_host_clk_edge.to_bool()) if (tile.Top__io_host_clk_edge.to_bool())
{ {
htif_phy.tick(tile.Top__io_host_in_ready.lo_word(), bool in_valid = tile.Top__io_host_in_ready.to_bool() &&
tile.Top__io_host_out_valid.lo_word(), htif->recv_nonblocking(&tile.Top__io_host_in_bits.values[0], htif_bits/8);
tile.Top__io_host_out_bits.lo_word()); tile.Top__io_host_in_valid = LIT<1>(in_valid);
tile.Top__io_host_out_ready = LIT<1>(1);
if (tile.Top__io_host_out_valid.to_bool())
htif->send(&tile.Top__io_host_out_bits.values[0], htif_bits/8);
} }
@ -152,7 +152,7 @@ int main(int argc, char** argv)
wb_insn.bits = wb_reg_inst; wb_insn.bits = wb_reg_inst;
std::string wb_disasm = disasm.disassemble(wb_insn); std::string wb_disasm = disasm.disassemble(wb_insn);
if (log || (quiet && trace_count % 10000 == 0)) if (log)
{ {
fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \ fprintf(logfile, "C: %10lld [%ld] pc=[%011lx] W[r%2ld=%016lx][%ld] R[r%2ld=%016lx] R[r%2ld=%016lx] inst=[%08lx] %-32s\n", \
(long long)trace_count, tile.Top_Tile_core_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_core_dpath__wb_reg_pc.lo_word(), \ (long long)trace_count, tile.Top_Tile_core_ctrl__wb_reg_valid.lo_word(), tile.Top_Tile_core_dpath__wb_reg_pc.lo_word(), \
@ -192,8 +192,5 @@ int main(int argc, char** argv)
return -1; return -1;
} }
close(tohost_fd);
close(fromhost_fd);
return 0; return 0;
} }

26
csrc/htif_emulator.h Normal file
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@ -0,0 +1,26 @@
#ifndef _HTIF_EMULATOR_H
#define _HTIF_EMULATOR_H
#include <fesvr/htif_pthread.h>
class htif_emulator_t : public htif_pthread_t
{
public:
htif_emulator_t(const std::vector<std::string>& args)
: htif_pthread_t(args)
{
}
void set_clock_divisor(int divisor, int hold_cycles)
{
write_cr(-1, 63, divisor | hold_cycles << 16);
}
void start()
{
set_clock_divisor(5, 2);
htif_pthread_t::start();
}
};
#endif

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@ -1,10 +1,16 @@
#include "htif_phy.h" #include "htif_emulator.h"
#include "mm.h" #include "mm.h"
#include "mm_dramsim2.h" #include "mm_dramsim2.h"
#include <DirectC.h> #include <DirectC.h>
#include <stdio.h>
#include <stdlib.h>
#include <vector>
#include <sstream>
#include <iterator>
htif_phy_t* htif_phy = NULL; static htif_emulator_t* htif = NULL;
mm_t* mm = NULL; static unsigned htif_bytes;
static mm_t* mm = NULL;
extern "C" { extern "C" {
@ -56,9 +62,8 @@ void memory_tick(
void htif_init void htif_init
( (
vc_handle fromhost,
vc_handle tohost,
vc_handle width, vc_handle width,
vc_handle argv,
vc_handle loadmem, vc_handle loadmem,
vc_handle dramsim vc_handle dramsim
) )
@ -66,17 +71,34 @@ void htif_init
mm = vc_getScalar(dramsim) ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t); mm = vc_getScalar(dramsim) ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
mm->init(MEM_SIZE); mm->init(MEM_SIZE);
vec32* fh = vc_4stVectorRef(fromhost);
vec32* th = vc_4stVectorRef(tohost);
vec32* w = vc_4stVectorRef(width); vec32* w = vc_4stVectorRef(width);
assert(w->d <= 32 && w->d % 8 == 0); // htif_tick assumes data fits in a vec32
htif_bytes = w->d/8;
char loadmem_str[1024]; char loadmem_str[1024];
vc_VectorToString(loadmem, loadmem_str); vc_VectorToString(loadmem, loadmem_str);
if (*loadmem_str) if (*loadmem_str)
load_mem(mm->get_data(), loadmem_str); load_mem(mm->get_data(), loadmem_str);
assert(w->d <= 32); // htif_tick assumes data fits in a vec32 char argv_str[1024];
htif_phy = new htif_phy_t(w->d, fh->d, th->d); vc_VectorToString(argv, argv_str);
if (!*argv_str)
{
if (*loadmem_str)
strcpy(argv_str, "none");
else
{
fprintf(stderr, "Usage: ./simv [host options] +argv=\"<target program> [target args]\"\n");
exit(-1);
}
}
std::vector<std::string> args;
std::stringstream ss(argv_str);
std::istream_iterator<std::string> begin(ss), end;
std::copy(begin, end, std::back_inserter<std::vector<std::string>>(args));
htif = new htif_emulator_t(args);
} }
void htif_tick void htif_tick
@ -86,19 +108,28 @@ void htif_tick
vc_handle htif_in_bits, vc_handle htif_in_bits,
vc_handle htif_out_valid, vc_handle htif_out_valid,
vc_handle htif_out_ready, vc_handle htif_out_ready,
vc_handle htif_out_bits vc_handle htif_out_bits,
vc_handle exit
) )
{ {
vec32* ob = vc_4stVectorRef(htif_out_bits); static bool peek_in_valid;
htif_phy->tick(vc_getScalar(htif_in_ready), vc_getScalar(htif_out_valid), ob->d); static uint32_t peek_in_bits;
if (vc_getScalar(htif_in_ready))
peek_in_valid = htif->recv_nonblocking(&peek_in_bits, htif_bytes);
vc_putScalar(htif_in_valid, htif_phy->in_valid()); vc_putScalar(htif_out_ready, 1);
vc_putScalar(htif_out_ready, htif_phy->out_ready()); if (vc_getScalar(htif_out_valid))
{
vec32* bits = vc_4stVectorRef(htif_out_bits);
htif->send(&bits->d, htif_bytes);
}
vec32 ib; vec32 bits = {0, 0};
ib.c = 0; bits.d = peek_in_bits;
ib.d = htif_phy->in_bits(); vc_put4stVector(htif_in_bits, &bits);
vc_put4stVector(htif_in_bits, &ib); vc_putScalar(htif_in_valid, peek_in_valid);
vc_putScalar(exit, htif->done() ? (htif->exit_code() << 1 | 1) : 0);
} }
} }

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@ -4,11 +4,13 @@ basedir = ..
include ../Makefrag include ../Makefrag
CXX := g++ CXX := g++
CXXFLAGS := -O1 -std=c++0x CXXFLAGS := $(CXXFLAGS) -O1 -std=c++0x -I$(RISCV)/include
CXXSRCS := emulator disasm mm mm_dramsim2 CXXSRCS := emulator disasm mm mm_dramsim2
CXXFLAGS := $(CXXFLAGS) -I$(basedir)/csrc -I$(basedir)/chisel/csrc -I$(basedir)/dramsim2 CXXFLAGS := $(CXXFLAGS) -I$(basedir)/csrc -I$(basedir)/chisel/csrc -I$(basedir)/dramsim2
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread
OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL)) OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL)) DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
@ -34,10 +36,10 @@ $(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(basedir)/csrc/%.cc $(basedir)/csr
$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $< $(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
emulator: $(OBJS) libdramsim.a emulator: $(OBJS) libdramsim.a
$(CXX) $(CXXFLAGS) -o $@ $(OBJS) -L. -ldramsim $(CXX) $(CXXFLAGS) -o $@ $(OBJS) $(LDFLAGS)
emulator-debug: $(DEBUG_OBJS) libdramsim.a emulator-debug: $(DEBUG_OBJS) libdramsim.a
$(CXX) $(CXXFLAGS) -o $@ $(DEBUG_OBJS) -L. -ldramsim $(CXX) $(CXXFLAGS) -o $@ $(DEBUG_OBJS) $(LDFLAGS)
clean: clean:
rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output
@ -67,13 +69,13 @@ output:
mkdir -p $@ mkdir -p $@
output/%.run: output/%.hex emulator output/%.run: output/%.hex emulator
fesvr +dramsim -c -testrun -m3000000 +loadmem=$< none 2> /dev/null ./emulator +dramsim +max-cycles=3000000 +loadmem=$< none 2> /dev/null
output/%.out: output/%.hex emulator output/%.out: output/%.hex emulator
fesvr +dramsim -c -testrun -m3000000 -l +loadmem=$< none 2> $@ ./emulator +dramsim +max-cycles=3000000 +verbose +loadmem=$< none 2> $@
output/%.vpd: output/%.hex emulator-debug output/%.vpd: output/%.hex emulator-debug
fesvr +dramsim -c./emulator-debug -testrun -m3000000 -l -v- +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@) | vcd2vpd - $@ > /dev/null && [ $$PIPESTATUS -eq 0 ] ./emulator-debug +dramsim +max-cycles=3000000 +verbose -v- +loadmem=$< none 2> $(patsubst %.vpd,%.out,$@) | vcd2vpd - $@ > /dev/null && [ $$PIPESTATUS -eq 0 ]
run-asm-tests: $(addprefix output/, $(addsuffix .out, $(global_asm_tests) $(global_asm_vm_tests))) run-asm-tests: $(addprefix output/, $(addsuffix .out, $(global_asm_tests) $(global_asm_vm_tests)))
@echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo; @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;

@ -1 +1 @@
Subproject commit 062076bd5826671871c710ad8ef89b2237626600 Subproject commit 2a91f23857ce35d59217a295202710be4ec8d5dc

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@ -4,6 +4,7 @@ import Chisel._
import Node._ import Node._
import uncore._ import uncore._
import rocket._ import rocket._
import rocket.Util._
import ReferenceChipBackend._ import ReferenceChipBackend._
import scala.collection.mutable.ArrayBuffer import scala.collection.mutable.ArrayBuffer
import scala.collection.mutable.HashMap import scala.collection.mutable.HashMap
@ -290,7 +291,11 @@ class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit
outmemsys.io.mem_backup_en <> io.mem_backup_en outmemsys.io.mem_backup_en <> io.mem_backup_en
// pad out the HTIF using a divided clock // pad out the HTIF using a divided clock
val hio = (new slowIO(8)) { Bits(width = htif_width+1) } val hio = (new SlowIO(512)) { Bits(width = htif_width+1) }
hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
hio.io.set_divisor.bits := htif.io.scr.wdata
htif.io.scr.rdata(63) := hio.io.divisor
hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid
hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits)) hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits))
htif.io.host.out.ready := hio.io.out_fast.ready htif.io.host.out.ready := hio.io.out_fast.ready

2
uncore

@ -1 +1 @@
Subproject commit 7270cf1702656098ffd217d28dac80ddc8c57a60 Subproject commit 871f7a86bc4540ca51ad397c8d29b6ea2363fd25