riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2 RAMModel: exploit latency to remove bypass

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-09-21 18:47:41 -07:00
parent e0ade8c5a9
commit 4066fbe18f
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/tilelink2/RAMModel.scala
View File

@ -104,7 +104,7 @@ class TLRAMModel extends LazyModule
a_flight.opcode := in.a.bits.opcode a_flight.opcode := in.a.bits.opcode
flight(in.a.bits.source) := a_flight flight(in.a.bits.source) := a_flight
val bypass = in.a.valid && in.a.bits.source === out.d.bits.source val bypass = if (edge.manager.minLatency > 0) Bool(false) else in.a.valid && in.a.bits.source === out.d.bits.source
val d_flight = RegNext(Mux(bypass, a_flight, flight(out.d.bits.source))) val d_flight = RegNext(Mux(bypass, a_flight, flight(out.d.bits.source)))
// Process A access requests // Process A access requests