From 4066fbe18f2e1cd995e399bb743b61c65aca61bd Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 21 Sep 2016 18:47:41 -0700 Subject: [PATCH] tilelink2 RAMModel: exploit latency to remove bypass --- src/main/scala/uncore/tilelink2/RAMModel.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/RAMModel.scala b/src/main/scala/uncore/tilelink2/RAMModel.scala index b872a849..bb8f983a 100644 --- a/src/main/scala/uncore/tilelink2/RAMModel.scala +++ b/src/main/scala/uncore/tilelink2/RAMModel.scala @@ -104,7 +104,7 @@ class TLRAMModel extends LazyModule a_flight.opcode := in.a.bits.opcode flight(in.a.bits.source) := a_flight - val bypass = in.a.valid && in.a.bits.source === out.d.bits.source + val bypass = if (edge.manager.minLatency > 0) Bool(false) else in.a.valid && in.a.bits.source === out.d.bits.source val d_flight = RegNext(Mux(bypass, a_flight, flight(out.d.bits.source))) // Process A access requests