riscv/rocket-chip
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fix wb bug

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This commit is contained in:
Henry Cook 2014-12-03 14:22:39 -08:00
parent 05b5188ad9
commit 404773eb9f
1 changed files with 4 additions and 3 deletions
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7
uncore/src/main/scala/cache.scala
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@ -462,6 +462,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
val crel_wb_src = Reg(init = UInt(0, width = log2Up(nClients))) val crel_wb_src = Reg(init = UInt(0, width = log2Up(nClients)))
val crel_wb_g_type = Reg(init = UInt(0, width = co.grantTypeWidth)) val crel_wb_g_type = Reg(init = UInt(0, width = co.grantTypeWidth))
val wb_buffer = Reg{xact.data.clone} val wb_buffer = Reg{xact.data.clone}
val addr_wb = Cat(xact_internal.meta.tag, xact.addr(untagBits-1,blockOffBits))
val release_count = Reg(init = UInt(0, width = log2Up(nClients+1))) val release_count = Reg(init = UInt(0, width = log2Up(nClients+1)))
val pending_probes = Reg(init = co.dir().flush) val pending_probes = Reg(init = co.dir().flush)
@ -476,8 +477,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) && io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) &&
(state != s_idle) //TODO: Also indexes (state != s_idle) //TODO: Also indexes
io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) && io.has_release_conflict := (co.isCoherenceConflict(xact.addr, c_rel.payload.addr) ||
(state != s_idle) //TODO: Also indexes? co.isCoherenceConflict(addr_wb, c_rel.payload.addr)) &&
(state != s_idle) //TODO: Also indexes?
val next_coh_on_release = co.masterMetadataOnRelease( val next_coh_on_release = co.masterMetadataOnRelease(
c_rel.payload, c_rel.payload,
@ -488,7 +490,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
xact_internal.meta.coh, xact_internal.meta.coh,
c_gnt.header.dst) c_gnt.header.dst)
val addr_wb = Cat(xact_internal.meta.tag, xact.addr(untagBits-1,blockOffBits))
val outer_write_acq = Bundle(UncachedWrite(xact.addr, UInt(trackerId), xact.data), val outer_write_acq = Bundle(UncachedWrite(xact.addr, UInt(trackerId), xact.data),
{ case TLId => outerId }) { case TLId => outerId })
val outer_write_wb = Bundle(UncachedWrite(addr_wb, UInt(trackerId), wb_buffer), val outer_write_wb = Bundle(UncachedWrite(addr_wb, UInt(trackerId), wb_buffer),