riscv/rocket-chip
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rocketchip: include devices from cbus in ConfigString

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This commit is contained in:
Wesley W. Terpstra 2016-10-27 18:03:43 -07:00
parent b68bc449e7
commit 401fd378b4
3 changed files with 9 additions and 13 deletions
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6
src/main/scala/coreplex/BaseCoreplex.scala
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@ -78,6 +78,12 @@ abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bund
abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) with HasCoreplexParameters { abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) with HasCoreplexParameters {
implicit val p = outer.p implicit val p = outer.p
// Create and export the ConfigString
val managers = outer.l1tol2.node.edgesIn(0).manager.managers
val configString = rocketchip.GenerateConfigString(p, managers)
println(s"\nGenerated Configuration String\n${configString}")
ConfigStringOutput.contents = Some(configString)
// Build a set of Tiles // Build a set of Tiles
val tiles = outer.lazyTiles.map(_.module) val tiles = outer.lazyTiles.map(_.module)
val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) } val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }

14
src/main/scala/rocketchip/BaseTop.scala
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@ -15,7 +15,6 @@ import coreplex._
// the following parameters will be refactored properly with TL2 // the following parameters will be refactored properly with TL2
case object GlobalAddrMap extends Field[AddrMap] case object GlobalAddrMap extends Field[AddrMap]
case object ConfigString extends Field[String]
case object NCoreplexExtClients extends Field[Int] case object NCoreplexExtClients extends Field[Int]
case object NExtInterrupts extends Field[Int] case object NExtInterrupts extends Field[Int]
/** Enable or disable monitoring of Diplomatic buses */ /** Enable or disable monitoring of Diplomatic buses */
@ -35,15 +34,10 @@ abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(impli
lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers
// Fill in the TL1 legacy parameters // Fill in the TL1 legacy parameters
val qWithSums = q.alterPartial { implicit val p = q.alterPartial {
case NCoreplexExtClients => pBusMasters.sum case NCoreplexExtClients => pBusMasters.sum
case NExtInterrupts => pInterrupts.sum case NExtInterrupts => pInterrupts.sum
} case GlobalAddrMap => GenerateGlobalAddrMap(q, peripheryManagers)
val qWithMap = qWithSums.alterPartial {
case GlobalAddrMap => GenerateGlobalAddrMap(qWithSums, peripheryManagers)
}
implicit val p = qWithMap.alterPartial {
case ConfigString => GenerateConfigString(qWithMap, peripheryManagers)
} }
val coreplex = LazyModule(buildCoreplex(p)) val coreplex = LazyModule(buildCoreplex(p))
@ -86,10 +80,6 @@ abstract class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]
println("\nGenerated Interrupt Vector") println("\nGenerated Interrupt Vector")
outer.pInterrupts.print outer.pInterrupts.print
println("\nGenerated Configuration String")
println(p(ConfigString))
ConfigStringOutput.contents = Some(p(ConfigString))
io.success := outer.coreplex.module.io.success io.success := outer.coreplex.module.io.success
} }

2
src/main/scala/rocketchip/Utils.scala
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@ -178,6 +178,6 @@ object GenerateBootROM {
require(rom.getInt(12) == 0, require(rom.getInt(12) == 0,
"Config string address position should not be occupied by code") "Config string address position should not be occupied by code")
rom.putInt(12, configStringAddr) rom.putInt(12, configStringAddr)
rom.array() ++ (p(ConfigString).getBytes.toSeq) rom.array() ++ (ConfigStringOutput.contents.get.getBytes.toSeq)
} }
} }