diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index 4f794a74..dead46fe 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -78,6 +78,12 @@ abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bund
 abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) with HasCoreplexParameters {
   implicit val p = outer.p
 
+  // Create and export the ConfigString
+  val managers = outer.l1tol2.node.edgesIn(0).manager.managers
+  val configString = rocketchip.GenerateConfigString(p, managers)
+  println(s"\nGenerated Configuration String\n${configString}")
+  ConfigStringOutput.contents = Some(configString)
+
   // Build a set of Tiles
   val tiles = outer.lazyTiles.map(_.module)
   val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index 10a2c1f1..6b57835c 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -15,7 +15,6 @@ import coreplex._
 
 // the following parameters will be refactored properly with TL2
 case object GlobalAddrMap extends Field[AddrMap]
-case object ConfigString extends Field[String]
 case object NCoreplexExtClients extends Field[Int]
 case object NExtInterrupts extends Field[Int]
 /** Enable or disable monitoring of Diplomatic buses */
@@ -35,15 +34,10 @@ abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(impli
   lazy val peripheryManagers = socBus.node.edgesIn(0).manager.managers
 
   // Fill in the TL1 legacy parameters
-  val qWithSums = q.alterPartial {
+  implicit val p = q.alterPartial {
     case NCoreplexExtClients => pBusMasters.sum
     case NExtInterrupts => pInterrupts.sum
-  }
-  val qWithMap = qWithSums.alterPartial {
-     case GlobalAddrMap => GenerateGlobalAddrMap(qWithSums, peripheryManagers)
-  }
-  implicit val p = qWithMap.alterPartial {
-    case ConfigString => GenerateConfigString(qWithMap, peripheryManagers)
+    case GlobalAddrMap => GenerateGlobalAddrMap(q, peripheryManagers)
   }
 
   val coreplex = LazyModule(buildCoreplex(p))
@@ -86,10 +80,6 @@ abstract class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]
   println("\nGenerated Interrupt Vector")
   outer.pInterrupts.print
 
-  println("\nGenerated Configuration String")
-  println(p(ConfigString))
-  ConfigStringOutput.contents = Some(p(ConfigString))
-
   io.success := outer.coreplex.module.io.success
 }
 
diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala
index c9c77771..33c59533 100644
--- a/src/main/scala/rocketchip/Utils.scala
+++ b/src/main/scala/rocketchip/Utils.scala
@@ -178,6 +178,6 @@ object GenerateBootROM {
     require(rom.getInt(12) == 0,
       "Config string address position should not be occupied by code")
     rom.putInt(12, configStringAddr)
-    rom.array() ++ (p(ConfigString).getBytes.toSeq)
+    rom.array() ++ (ConfigStringOutput.contents.get.getBytes.toSeq)
   }
 }