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coreplex: provide coherence managers with geometry information

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Wesley W. Terpstra 2017-01-22 11:06:20 -08:00 committed by Henry Cook
parent d4b3a0f0be
commit 3fc55298ef
3 changed files with 8 additions and 6 deletions
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3
src/main/scala/coreplex/BaseCoreplex.scala
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@ -22,10 +22,11 @@ case class BroadcastConfig(
case object BroadcastConfig extends Field[BroadcastConfig] case object BroadcastConfig extends Field[BroadcastConfig]
/** L2 memory subsystem configuration */ /** L2 memory subsystem configuration */
case class BankedL2Geometry(bank: Int, banks: Int, channel: Int, channels: Int)
case class BankedL2Config( case class BankedL2Config(
nMemoryChannels: Int = 1, nMemoryChannels: Int = 1,
nBanksPerChannel: Int = 1, nBanksPerChannel: Int = 1,
coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case q => coherenceManager: (Parameters, CoreplexNetwork, BankedL2Geometry) => (TLInwardNode, TLOutwardNode) = { case (q, _, _) =>
implicit val p = q implicit val p = q
val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig) val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless)) val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))

2
src/main/scala/coreplex/Configs.scala
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@ -143,7 +143,7 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
* DO NOT use this configuration. * DO NOT use this configuration.
*/ */
class WithStatelessBridge extends Config((site, here, up) => { class WithStatelessBridge extends Config((site, here, up) => {
case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case q => case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _, _) =>
implicit val p = q implicit val p = q
val cork = LazyModule(new TLCacheCork(unsafe = true)) val cork = LazyModule(new TLCacheCork(unsafe = true))
(cork.node, TLWidthWidget(p(L1toL2Config).beatBytes)(cork.node)) (cork.node, TLWidthWidget(p(L1toL2Config).beatBytes)(cork.node))

9
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -70,15 +70,16 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
require (isPow2(l1tol2_lineBytes)) require (isPow2(l1tol2_lineBytes))
val mem = TLOutputNode() val mem = TLOutputNode()
for (i <- 0 until l2Config.nMemoryChannels) { for (channel <- 0 until l2Config.nMemoryChannels) {
val bankBar = LazyModule(new TLXbar) val bankBar = LazyModule(new TLXbar)
mem := bankBar.node mem := bankBar.node
val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes) val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
for (i <- 0 until l2Config.nBanksPerChannel) { for (bank <- 0 until l2Config.nBanksPerChannel) {
val (in, out) = l2Config.coherenceManager(p) val geometry = BankedL2Geometry(bank, l2Config.nBanksPerChannel, channel, l2Config.nMemoryChannels)
val (in, out) = l2Config.coherenceManager(p, this, geometry)
in := l1tol2.node in := l1tol2.node
bankBar.node := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(out) bankBar.node := TLFilter(AddressSet(bank * l1tol2_lineBytes, mask))(out)
} }
} }
} }