From 3fc55298ef7312ea05ff131217949eac76730ddb Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sun, 22 Jan 2017 11:06:20 -0800 Subject: [PATCH] coreplex: provide coherence managers with geometry information --- src/main/scala/coreplex/BaseCoreplex.scala | 3 ++- src/main/scala/coreplex/Configs.scala | 2 +- src/main/scala/coreplex/CoreplexNetwork.scala | 9 +++++---- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 94c43fa7..18d25d80 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -22,10 +22,11 @@ case class BroadcastConfig( case object BroadcastConfig extends Field[BroadcastConfig] /** L2 memory subsystem configuration */ +case class BankedL2Geometry(bank: Int, banks: Int, channel: Int, channels: Int) case class BankedL2Config( nMemoryChannels: Int = 1, nBanksPerChannel: Int = 1, - coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case q => + coherenceManager: (Parameters, CoreplexNetwork, BankedL2Geometry) => (TLInwardNode, TLOutwardNode) = { case (q, _, _) => implicit val p = q val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig) val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless)) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index bd09cf20..0c94b128 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -143,7 +143,7 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => { * DO NOT use this configuration. */ class WithStatelessBridge extends Config((site, here, up) => { - case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case q => + case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _, _) => implicit val p = q val cork = LazyModule(new TLCacheCork(unsafe = true)) (cork.node, TLWidthWidget(p(L1toL2Config).beatBytes)(cork.node)) diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala index 81edd50a..d89c66f6 100644 --- a/src/main/scala/coreplex/CoreplexNetwork.scala +++ b/src/main/scala/coreplex/CoreplexNetwork.scala @@ -70,15 +70,16 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork { require (isPow2(l1tol2_lineBytes)) val mem = TLOutputNode() - for (i <- 0 until l2Config.nMemoryChannels) { + for (channel <- 0 until l2Config.nMemoryChannels) { val bankBar = LazyModule(new TLXbar) mem := bankBar.node val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes) - for (i <- 0 until l2Config.nBanksPerChannel) { - val (in, out) = l2Config.coherenceManager(p) + for (bank <- 0 until l2Config.nBanksPerChannel) { + val geometry = BankedL2Geometry(bank, l2Config.nBanksPerChannel, channel, l2Config.nMemoryChannels) + val (in, out) = l2Config.coherenceManager(p, this, geometry) in := l1tol2.node - bankBar.node := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(out) + bankBar.node := TLFilter(AddressSet(bank * l1tol2_lineBytes, mask))(out) } } }