riscv/rocket-chip
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Make blocking L1 D$ the default

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The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
This commit is contained in:
Andrew Waterman 2017-03-15 15:23:30 -07:00
parent 487b8db5ef
commit 3ea822c2cf
2 changed files with 4 additions and 4 deletions
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6
src/main/scala/coreplex/Configs.scala
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@ -41,7 +41,7 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
divEarlyOut = true))),
dcache = Some(DCacheParams(
rowBits = site(L1toL2Config).beatBytes*8,
nMSHRs = 2,
nMSHRs = 0,
blockBytes = site(CacheBlockBytes))),
icache = Some(ICacheParams(
rowBits = site(L1toL2Config).beatBytes*8,
@ -147,9 +147,9 @@ class WithRV32 extends Config((site, here, up) => {
}
})
class WithBlockingL1 extends Config((site, here, up) => {
class WithNonblockingL1(nMSHRs: Int) extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(dcache = r.dcache.map(_.copy(nMSHRs = 0)))
r.copy(dcache = r.dcache.map(_.copy(nMSHRs = nMSHRs)))
}
})

2
src/main/scala/rocketchip/Configs.scala
View File

@ -46,7 +46,7 @@ class BasePlatformConfig extends Config((site, here, up) => {
/** Actual elaboratable target Configs */
class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
class DefaultConfig extends Config(new WithBlockingL1 ++ new WithNBigCores(1) ++ new BaseConfig)
class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig)
class DefaultL2Config extends Config(new WithL2Cache ++ new WithNBigCores(1) ++ new BaseConfig)
class DefaultBufferlessConfig extends Config(