diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index ece3aaa8..92a48115 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -41,7 +41,7 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
         divEarlyOut = true))),
       dcache = Some(DCacheParams(
         rowBits = site(L1toL2Config).beatBytes*8,
-        nMSHRs  = 2,
+        nMSHRs  = 0,
         blockBytes = site(CacheBlockBytes))),
       icache = Some(ICacheParams(
         rowBits = site(L1toL2Config).beatBytes*8,
@@ -147,9 +147,9 @@ class WithRV32 extends Config((site, here, up) => {
   }
 })
 
-class WithBlockingL1 extends Config((site, here, up) => {
+class WithNonblockingL1(nMSHRs: Int) extends Config((site, here, up) => {
   case RocketTilesKey => up(RocketTilesKey, site) map { r =>
-    r.copy(dcache = r.dcache.map(_.copy(nMSHRs = 0)))
+    r.copy(dcache = r.dcache.map(_.copy(nMSHRs = nMSHRs)))
   }
 })
 
diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index e3f8fe57..2d4a2081 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -46,7 +46,7 @@ class BasePlatformConfig extends Config((site, here, up) => {
 /** Actual elaboratable target Configs */
 
 class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
-class DefaultConfig extends Config(new WithBlockingL1 ++ new WithNBigCores(1) ++ new BaseConfig)
+class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig)
 
 class DefaultL2Config extends Config(new WithL2Cache ++ new WithNBigCores(1) ++ new BaseConfig)
 class DefaultBufferlessConfig extends Config(