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Merge pull request #2 from ucb-bar/chisel3

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Pass a BitPat to Lookup
This commit is contained in:
Andrew Waterman 2016-03-06 04:27:52 -08:00
commit 3e721fe80b
1 changed files with 1 additions and 1 deletions
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groundtest/src/main/scala/tracegen.scala
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@ -133,7 +133,7 @@ class TagMan(val logNumTags : Int) extends Module {
val inUse = List.fill(numTags)(Reg(init = Bool(false))) val inUse = List.fill(numTags)(Reg(init = Bool(false)))
// Mapping from each tag to its 'inUse' bit // Mapping from each tag to its 'inUse' bit
val inUseMap = (0 to numTags-1).map(i => UInt(i, logNumTags)).zip(inUse) val inUseMap = (0 to numTags-1).map(i => BitPat(UInt(i))).zip(inUse)
// Next tag to offer // Next tag to offer
val nextTag = Reg(init = UInt(0, logNumTags)) val nextTag = Reg(init = UInt(0, logNumTags))