make sure MixedAllocPutRegression uses a block that hasn't been cached already
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fe8d81958f
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@ -181,21 +181,23 @@ class MixedAllocPutRegression(implicit p: Parameters) extends Regression()(p) {
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val put_beat = Vec(UInt(0), UInt(0), UInt(2))
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val put_beat = Vec(UInt(0), UInt(0), UInt(2))
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val (put_acq_id, put_acq_done) = Counter(
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val (put_acq_id, put_acq_done) = Counter(
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state === s_put_send && io.mem.acquire.ready, 3)
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state === s_put_send && io.mem.acquire.ready, put_data.size)
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val (put_gnt_cnt, put_gnt_done) = Counter(
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val (put_gnt_cnt, put_gnt_done) = Counter(
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state === s_put_wait && io.mem.grant.valid, 3)
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state === s_put_wait && io.mem.grant.valid, put_data.size)
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val get_data = Vec(UInt("h2222222211111111"), UInt("h3333333333333333"))
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val get_data = Vec(UInt("h2222222211111111"), UInt("h3333333333333333"))
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val get_beat = Vec(UInt(0), UInt(2))
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val get_beat = Vec(UInt(0), UInt(2))
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val (get_acq_id, get_acq_done) = Counter(
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val (get_acq_id, get_acq_done) = Counter(
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state === s_get_send && io.mem.acquire.ready, 2)
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state === s_get_send && io.mem.acquire.ready, get_data.size)
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val (get_gnt_cnt, get_gnt_done) = Counter(
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val (get_gnt_cnt, get_gnt_done) = Counter(
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state === s_get_wait && io.mem.grant.valid, 2)
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state === s_get_wait && io.mem.grant.valid, get_data.size)
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val blockAddr = memStartBlock + 15
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val put_acquire = Put(
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val put_acquire = Put(
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client_xact_id = put_acq_id,
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client_xact_id = put_acq_id,
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addr_block = UInt(memStartBlock),
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addr_block = UInt(blockAddr),
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addr_beat = put_beat(put_acq_id),
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addr_beat = put_beat(put_acq_id),
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data = put_data(put_acq_id),
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data = put_data(put_acq_id),
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wmask = put_wmask(put_acq_id),
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wmask = put_wmask(put_acq_id),
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@ -203,7 +205,7 @@ class MixedAllocPutRegression(implicit p: Parameters) extends Regression()(p) {
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val get_acquire = Get(
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val get_acquire = Get(
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client_xact_id = get_acq_id,
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client_xact_id = get_acq_id,
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addr_block = UInt(memStartBlock),
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addr_block = UInt(blockAddr),
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addr_beat = get_beat(get_acq_id))
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addr_beat = get_beat(get_acq_id))
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io.mem.acquire.valid := (state === s_put_send) || (state === s_get_send)
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io.mem.acquire.valid := (state === s_put_send) || (state === s_get_send)
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