riscv/rocket-chip
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Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release,

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but would otherwise be allocated.

Closes #45
This commit is contained in:
Colin Schmidt 2016-05-19 10:55:00 -07:00 committed by Henry Cook
parent fd83d20857
commit 3e0b5d6fd9
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/uncore.scala
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@ -87,7 +87,7 @@ trait HasCoherenceAgentWiringHelpers {
val match_ok = matchOverride.getOrElse(Bool(true)) val match_ok = matchOverride.getOrElse(Bool(true))
in.ready := Mux(no_matches, ready_bits.orR, (match_bits & ready_bits).orR) && alloc_ok && match_ok in.ready := Mux(no_matches, ready_bits.orR, (match_bits & ready_bits).orR) && alloc_ok && match_ok
outs.zip(allocs).zipWithIndex.foreach { case((out, a), i) => outs.zip(allocs).zipWithIndex.foreach { case((out, a), i) =>
out.valid := in.valid && match_ok out.valid := in.valid && match_ok && alloc_ok
out.bits := in.bits out.bits := in.bits
dataOverrides foreach { d => out.bits.data := d(i) } dataOverrides foreach { d => out.bits.data := d(i) }
a := alloc_bits(i) & no_matches & alloc_ok a := alloc_bits(i) & no_matches & alloc_ok