riscv/rocket-chip
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regmapper: remove the Pipe in the RegMapper Queue

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With this pipe here, devices which declare concurrency > 0
actually accept transactions on the same cycle they complete
the previous one. This is unexpected behavior.
This commit is contained in:
Megan Wachs 2017-04-19 18:57:23 -07:00
parent b4d17c76d1
commit 3dfd584075
1 changed files with 1 additions and 1 deletions
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src/main/scala/regmapper/RegMapper.scala
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@ -62,7 +62,7 @@ object RegMapper
val depth = concurrency
require (depth >= 0)
require (!pipelined || depth > 0, "Register-based device with request/response handshaking needs concurrency > 0")
val back = if (depth > 0) Queue(front, depth, pipe = depth == 1) else front
val back = if (depth > 0) Queue(front, depth) else front
// Convert to and from Bits
def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =