riscv/rocket-chip
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rocketchip: replace TL1 MMIO with an example of TL2 MMIO

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This commit is contained in:
Wesley W. Terpstra
2016-10-25 16:27:42 -07:00
parent 650f6fb23f
commit 3df797fcab
5 changed files with 30 additions and 72 deletions
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src/main/scala/rocketchip/Utils.scala
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@ -90,7 +90,7 @@ object GenerateGlobalAddrMap {
}).flatten.toList
lazy val tl2AddrMap = new AddrMap(uniquelyNamedTL2Devices, collapse = true)
lazy val pBusIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: p(ExtMMIOPorts), collapse = true)
lazy val pBusIOAddrMap = new AddrMap(Seq(AddrMapEntry("TL2", tl2AddrMap)), collapse = true)
val memBase = 0x80000000L
val memSize = p(ExtMemSize)