riscv/rocket-chip
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rocketchip: replace TL1 MMIO with an example of TL2 MMIO

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This commit is contained in:
Wesley W. Terpstra
2016-10-25 16:27:42 -07:00
parent 650f6fb23f
commit 3df797fcab
5 changed files with 30 additions and 72 deletions
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6
src/main/scala/rocketchip/ExampleTop.scala
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@ -15,7 +15,7 @@ class ExampleTop(q: Parameters) extends BaseTop(q)
with PeripheryExtInterrupts
with PeripheryCoreplexLocalInterrupter
with PeripheryMasterMem
with PeripheryMasterMMIO
with PeripheryMasterAXI4MMIO
with PeripherySlave {
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, this)))
}
@ -26,7 +26,7 @@ class ExampleTopBundle[+L <: ExampleTop](p: Parameters, l: L) extends BaseTopBun
with PeripheryExtInterruptsBundle
with PeripheryCoreplexLocalInterrupterBundle
with PeripheryMasterMemBundle
with PeripheryMasterMMIOBundle
with PeripheryMasterAXI4MMIOBundle
with PeripherySlaveBundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](p: Parameters, l: L, b: B) extends BaseTopModule(p, l, b)
@ -35,7 +35,7 @@ class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](p: Parameter
with PeripheryExtInterruptsModule
with PeripheryCoreplexLocalInterrupterModule
with PeripheryMasterMemModule
with PeripheryMasterMMIOModule
with PeripheryMasterAXI4MMIOModule
with PeripherySlaveModule
with HardwiredResetVector
with DirectConnection