riscv/rocket-chip
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rocketchip: replace TL1 MMIO with an example of TL2 MMIO

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This commit is contained in:
Wesley W. Terpstra
2016-10-25 16:27:42 -07:00
parent 650f6fb23f
commit 3df797fcab
5 changed files with 30 additions and 72 deletions
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16
src/main/scala/rocketchip/Configs.scala
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@ -48,11 +48,6 @@ class BasePlatformConfig extends Config(
// Note that PLIC asserts that this is > 0.
case AsyncDebugBus => false
case IncludeJtagDTM => false
case AsyncMMIOChannels => false
case ExtMMIOPorts => Nil
case NExtMMIOAXIChannels => 0
case NExtMMIOAHBChannels => 0
case NExtMMIOTLChannels => 0
case AsyncBusChannels => false
case NExtBusAXIChannels => 0
case HastiId => "Ext"
@ -110,17 +105,6 @@ class WithExtMemSize(n: Long) extends Config(
case _ => throw new CDEMatchError
}
)
class WithAHB extends Config(
(pname, site, here) => pname match {
case TMemoryChannels => BusType.AHB
case NExtMMIOAHBChannels => 1
})
class WithTL extends Config(
(pname, site, here) => pname match {
case TMemoryChannels => BusType.TL
case NExtMMIOTLChannels => 1
})
class WithScratchpads extends Config(new WithNMemoryChannels(0) ++ new WithDataScratchpad(16384))