riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

workaround for Chisel3 name-aliasing issue

Browse Source
This commit is contained in:
Howard Mao 2016-03-30 19:15:22 -07:00
parent 8e7f18084b
commit 3d990bdbef
1 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
uncore/src/main/scala/cache.scala
View File

@ -625,9 +625,9 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
val xact_op_code = Reg{ UInt() } val xact_op_code = Reg{ UInt() }
val xact_addr_byte = Reg{ UInt() } val xact_addr_byte = Reg{ UInt() }
val xact_op_size = Reg{ UInt() } val xact_op_size = Reg{ UInt() }
val xact_vol_irel_r_type = Reg{ io.irel().r_type } val xact_vol_ir_r_type = Reg{ io.irel().r_type }
val xact_vol_irel_src = Reg{ io.irel().client_id } val xact_vol_ir_src = Reg{ io.irel().client_id }
val xact_vol_irel_client_xact_id = Reg{ io.irel().client_xact_id } val xact_vol_ir_client_xact_id = Reg{ io.irel().client_xact_id }
// Miss queue holds transaction metadata used to make grants // Miss queue holds transaction metadata used to make grants
val ignt_q = Module(new Queue( val ignt_q = Module(new Queue(
@ -639,10 +639,10 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
val xact_addr_idx = xact_addr_block(idxMSB,idxLSB) val xact_addr_idx = xact_addr_block(idxMSB,idxLSB)
val xact_addr_tag = xact_addr_block >> UInt(tagLSB) val xact_addr_tag = xact_addr_block >> UInt(tagLSB)
val xact_vol_irel = Release( val xact_vol_irel = Release(
src = xact_vol_irel_src, src = xact_vol_ir_src,
voluntary = Bool(true), voluntary = Bool(true),
r_type = xact_vol_irel_r_type, r_type = xact_vol_ir_r_type,
client_xact_id = xact_vol_irel_client_xact_id, client_xact_id = xact_vol_ir_client_xact_id,
addr_block = xact_addr_block) addr_block = xact_addr_block)
(p.alterPartial({ case TLId => p(InnerTLId) })) (p.alterPartial({ case TLId => p(InnerTLId) }))
@ -876,9 +876,9 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
updatePendingCohWhen(io.inner.release.fire(), pending_coh_on_irel) updatePendingCohWhen(io.inner.release.fire(), pending_coh_on_irel)
mergeDataInner(io.inner.release) mergeDataInner(io.inner.release)
when(io.inner.release.fire() && irel_can_merge) { when(io.inner.release.fire() && irel_can_merge) {
xact_vol_irel_r_type := io.irel().r_type xact_vol_ir_r_type := io.irel().r_type
xact_vol_irel_src := io.irel().client_id xact_vol_ir_src := io.irel().client_id
xact_vol_irel_client_xact_id := io.irel().client_xact_id xact_vol_ir_client_xact_id := io.irel().client_xact_id
} }
// Handle misses or coherence permission upgrades by initiating a new transaction in the outer memory: // Handle misses or coherence permission upgrades by initiating a new transaction in the outer memory:
@ -1112,19 +1112,19 @@ class L2WritebackUnit(trackerId: Int)(implicit p: Parameters) extends L2XactTrac
val xact = Reg(new L2WritebackReq) val xact = Reg(new L2WritebackReq)
val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits))) val data_buffer = Reg(init=Vec.fill(innerDataBeats)(UInt(0, width = innerDataBits)))
val xact_vol_irel_r_type = Reg{ io.irel().r_type } val xact_vol_ir_r_type = Reg{ io.irel().r_type }
val xact_vol_irel_src = Reg{ io.irel().client_id } val xact_vol_ir_src = Reg{ io.irel().client_id }
val xact_vol_irel_client_xact_id = Reg{ io.irel().client_xact_id } val xact_vol_ir_client_xact_id = Reg{ io.irel().client_xact_id }
val xact_addr_block = if (cacheIdBits == 0) val xact_addr_block = if (cacheIdBits == 0)
Cat(xact.tag, xact.idx) Cat(xact.tag, xact.idx)
else else
Cat(xact.tag, xact.idx, UInt(cacheId, cacheIdBits)) Cat(xact.tag, xact.idx, UInt(cacheId, cacheIdBits))
val xact_vol_irel = Release( val xact_vol_irel = Release(
src = xact_vol_irel_src, src = xact_vol_ir_src,
voluntary = Bool(true), voluntary = Bool(true),
r_type = xact_vol_irel_r_type, r_type = xact_vol_ir_r_type,
client_xact_id = xact_vol_irel_client_xact_id, client_xact_id = xact_vol_ir_client_xact_id,
addr_block = xact_addr_block) addr_block = xact_addr_block)
val pending_irels = connectTwoWayBeatCounter( val pending_irels = connectTwoWayBeatCounter(
@ -1189,9 +1189,9 @@ class L2WritebackUnit(trackerId: Int)(implicit p: Parameters) extends L2XactTrac
xact.coh := pending_coh_on_irel xact.coh := pending_coh_on_irel
when(io.irel().hasData()) { data_buffer(io.irel().addr_beat) := io.irel().data } when(io.irel().hasData()) { data_buffer(io.irel().addr_beat) := io.irel().data }
when(irel_can_merge) { when(irel_can_merge) {
xact_vol_irel_r_type := io.irel().r_type xact_vol_ir_r_type := io.irel().r_type
xact_vol_irel_src := io.irel().client_id xact_vol_ir_src := io.irel().client_id
xact_vol_irel_client_xact_id := io.irel().client_xact_id xact_vol_ir_client_xact_id := io.irel().client_xact_id
} }
} }