riscv/rocket-chip
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Set misa.base = 1 for RV32

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This commit is contained in:
Andrew Waterman 2016-07-07 15:30:23 -07:00
parent 2455a806af
commit 3d8939d3c3
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/csr.scala
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@ -241,7 +241,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
(if (usingAtomics) "A" else "") + (if (usingAtomics) "A" else "") +
(if (usingFPU) "FD" else "") + (if (usingFPU) "FD" else "") +
(if (usingRoCC) "X" else "") (if (usingRoCC) "X" else "")
val isa = ((if (xLen == 32) BigInt(0) else BigInt(2)) << (xLen-2)) | val isa = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) |
isa_string.map(x => 1 << (x - 'A')).reduce(_|_) isa_string.map(x => 1 << (x - 'A')).reduce(_|_)
val read_mstatus = io.status.toBits()(xLen-1,0) val read_mstatus = io.status.toBits()(xLen-1,0)