1
0

coreplex: configString is a property of the RISCVPlatform

This commit is contained in:
Wesley W. Terpstra 2016-11-21 16:11:16 -08:00
parent e8be365b5d
commit 3d644b943c
5 changed files with 25 additions and 28 deletions

View File

@ -105,7 +105,6 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
implicit val p = outer.p implicit val p = outer.p
{
println("\nGenerated Address Map") println("\nGenerated Address Map")
for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) { for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) {
val prot = (if (manager.supportsGet) "R" else "") + val prot = (if (manager.supportsGet) "R" else "") +
@ -117,7 +116,6 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
} }
} }
} }
}
trait BankedL2CoherenceManagers extends CoreplexNetwork { trait BankedL2CoherenceManagers extends CoreplexNetwork {
val module: BankedL2CoherenceManagersModule val module: BankedL2CoherenceManagersModule

View File

@ -26,6 +26,11 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
plic.intnode := intBar.intnode plic.intnode := intBar.intnode
lazy val configString = {
val managers = l1tol2.node.edgesIn(0).manager.managers
rocketchip.GenerateConfigString(p, clint, plic, managers)
}
} }
trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle { trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle {
@ -48,14 +53,6 @@ trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule {
val rtcLast = Reg(init = Bool(false), next=rtcSync) val rtcLast = Reg(init = Bool(false), next=rtcSync)
outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast))) outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast)))
{ println(s"\nGenerated Configuration String\n${outer.configString}")
val managers = outer.l1tol2.node.edgesIn(0).manager.managers ConfigStringOutput.contents = Some(outer.configString)
// Allow something else to have override the config string
if (!ConfigStringOutput.contents.isDefined) {
ConfigStringOutput.contents = Some(rocketchip.GenerateConfigString(p, outer.clint, outer.plic, managers))
}
println(s"\nGenerated Configuration String\n${ConfigStringOutput.contents.get}")
}
} }

View File

@ -11,7 +11,6 @@ import rocketchip._
/** Example Top with Periphery */ /** Example Top with Periphery */
class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex) class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex)
with DirectConnection with DirectConnection
with PeripheryBootROM
with PeripheryExtInterrupts with PeripheryExtInterrupts
with PeripheryMasterAXI4Mem with PeripheryMasterAXI4Mem
with PeripheryMasterAXI4MMIO { with PeripheryMasterAXI4MMIO {
@ -19,18 +18,17 @@ class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Par
} }
class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer) class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer)
with PeripheryBootROMBundle
with PeripheryExtInterruptsBundle with PeripheryExtInterruptsBundle
with PeripheryMasterAXI4MemBundle with PeripheryMasterAXI4MemBundle
with PeripheryMasterAXI4MMIOBundle with PeripheryMasterAXI4MMIOBundle
class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io) class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
with PeripheryBootROMModule
with PeripheryExtInterruptsModule with PeripheryExtInterruptsModule
with PeripheryMasterAXI4MemModule with PeripheryMasterAXI4MemModule
with PeripheryMasterAXI4MMIOModule with PeripheryMasterAXI4MMIOModule
class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex) class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex)
with PeripheryBootROM
with PeripheryDTM with PeripheryDTM
with PeripheryCounter with PeripheryCounter
with HardwiredResetVector { with HardwiredResetVector {
@ -38,11 +36,13 @@ class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implic
} }
class ExampleRocketTopBundle[+L <: ExampleRocketTop[DefaultCoreplex]](_outer: L) extends ExampleTopBundle(_outer) class ExampleRocketTopBundle[+L <: ExampleRocketTop[DefaultCoreplex]](_outer: L) extends ExampleTopBundle(_outer)
with PeripheryBootROMBundle
with PeripheryDTMBundle with PeripheryDTMBundle
with PeripheryCounterBundle with PeripheryCounterBundle
with HardwiredResetVectorBundle with HardwiredResetVectorBundle
class ExampleRocketTopModule[+L <: ExampleRocketTop[DefaultCoreplex], +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io) class ExampleRocketTopModule[+L <: ExampleRocketTop[DefaultCoreplex], +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
with PeripheryBootROMModule
with PeripheryDTMModule with PeripheryDTMModule
with PeripheryCounterModule with PeripheryCounterModule
with HardwiredResetVectorModule with HardwiredResetVectorModule

View File

@ -156,10 +156,12 @@ trait PeripheryMasterAXI4MMIOModule {
trait PeripheryBootROM { trait PeripheryBootROM {
this: TopNetwork => this: TopNetwork =>
val coreplex: CoreplexRISCVPlatform
val bootrom_address = 0x1000 private val bootrom_address = 0x1000
val bootrom_size = 0x1000 private val bootrom_size = 0x1000
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, GenerateBootROM(p, bootrom_address), true, peripheryBusConfig.beatBytes)) private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.configString)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
} }

View File

@ -84,7 +84,7 @@ object GenerateConfigString {
} }
object GenerateBootROM { object GenerateBootROM {
def apply(p: Parameters, address: BigInt) = { def apply(p: Parameters, address: BigInt, configString: String) = {
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile))) val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
val rom = ByteBuffer.wrap(romdata) val rom = ByteBuffer.wrap(romdata)
@ -95,6 +95,6 @@ object GenerateBootROM {
require(rom.getInt(12) == 0, require(rom.getInt(12) == 0,
"Config string address position should not be occupied by code") "Config string address position should not be occupied by code")
rom.putInt(12, configStringAddr) rom.putInt(12, configStringAddr)
rom.array() ++ (ConfigStringOutput.contents.get.getBytes.toSeq) rom.array() ++ (configString.getBytes.toSeq)
} }
} }