From 3d644b943cf59408d4f5fd9b526e9ede4139c1f7 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 21 Nov 2016 16:11:16 -0800 Subject: [PATCH] coreplex: configString is a property of the RISCVPlatform --- src/main/scala/coreplex/BaseCoreplex.scala | 18 ++++++++---------- src/main/scala/coreplex/RISCVPlatform.scala | 17 +++++++---------- src/main/scala/rocketchip/ExampleTop.scala | 6 +++--- src/main/scala/rocketchip/Periphery.scala | 8 +++++--- src/main/scala/rocketchip/Utils.scala | 4 ++-- 5 files changed, 25 insertions(+), 28 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index dd9b9c6e..75325802 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -105,16 +105,14 @@ trait CoreplexNetworkModule extends HasCoreplexParameters { implicit val p = outer.p - { - println("\nGenerated Address Map") - for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) { - val prot = (if (manager.supportsGet) "R" else "") + - (if (manager.supportsPutFull) "W" else "") + - (if (manager.executable) "X" else "") + - (if (manager.supportsAcquire) " [C]" else "") - manager.address.foreach { a => - println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot") - } + println("\nGenerated Address Map") + for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) { + val prot = (if (manager.supportsGet) "R" else "") + + (if (manager.supportsPutFull) "W" else "") + + (if (manager.executable) "X" else "") + + (if (manager.supportsAcquire) " [C]" else "") + manager.address.foreach { a => + println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot") } } } diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala index e379aaeb..804854d4 100644 --- a/src/main/scala/coreplex/RISCVPlatform.scala +++ b/src/main/scala/coreplex/RISCVPlatform.scala @@ -26,6 +26,11 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork { clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) plic.intnode := intBar.intnode + + lazy val configString = { + val managers = l1tol2.node.edgesIn(0).manager.managers + rocketchip.GenerateConfigString(p, clint, plic, managers) + } } trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle { @@ -48,14 +53,6 @@ trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule { val rtcLast = Reg(init = Bool(false), next=rtcSync) outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast))) - { - val managers = outer.l1tol2.node.edgesIn(0).manager.managers - - // Allow something else to have override the config string - if (!ConfigStringOutput.contents.isDefined) { - ConfigStringOutput.contents = Some(rocketchip.GenerateConfigString(p, outer.clint, outer.plic, managers)) - } - - println(s"\nGenerated Configuration String\n${ConfigStringOutput.contents.get}") - } + println(s"\nGenerated Configuration String\n${outer.configString}") + ConfigStringOutput.contents = Some(outer.configString) } diff --git a/src/main/scala/rocketchip/ExampleTop.scala b/src/main/scala/rocketchip/ExampleTop.scala index a8ff4adf..00cafe31 100644 --- a/src/main/scala/rocketchip/ExampleTop.scala +++ b/src/main/scala/rocketchip/ExampleTop.scala @@ -11,7 +11,6 @@ import rocketchip._ /** Example Top with Periphery */ class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex) with DirectConnection - with PeripheryBootROM with PeripheryExtInterrupts with PeripheryMasterAXI4Mem with PeripheryMasterAXI4MMIO { @@ -19,18 +18,17 @@ class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Par } class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer) - with PeripheryBootROMBundle with PeripheryExtInterruptsBundle with PeripheryMasterAXI4MemBundle with PeripheryMasterAXI4MMIOBundle class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io) - with PeripheryBootROMModule with PeripheryExtInterruptsModule with PeripheryMasterAXI4MemModule with PeripheryMasterAXI4MMIOModule class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex) + with PeripheryBootROM with PeripheryDTM with PeripheryCounter with HardwiredResetVector { @@ -38,11 +36,13 @@ class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implic } class ExampleRocketTopBundle[+L <: ExampleRocketTop[DefaultCoreplex]](_outer: L) extends ExampleTopBundle(_outer) + with PeripheryBootROMBundle with PeripheryDTMBundle with PeripheryCounterBundle with HardwiredResetVectorBundle class ExampleRocketTopModule[+L <: ExampleRocketTop[DefaultCoreplex], +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io) + with PeripheryBootROMModule with PeripheryDTMModule with PeripheryCounterModule with HardwiredResetVectorModule diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index aaf6fd4f..3cc38035 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -156,10 +156,12 @@ trait PeripheryMasterAXI4MMIOModule { trait PeripheryBootROM { this: TopNetwork => + val coreplex: CoreplexRISCVPlatform - val bootrom_address = 0x1000 - val bootrom_size = 0x1000 - val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, GenerateBootROM(p, bootrom_address), true, peripheryBusConfig.beatBytes)) + private val bootrom_address = 0x1000 + private val bootrom_size = 0x1000 + private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.configString) + val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes)) bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) } diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala index f8b3e3f4..bcf54049 100644 --- a/src/main/scala/rocketchip/Utils.scala +++ b/src/main/scala/rocketchip/Utils.scala @@ -84,7 +84,7 @@ object GenerateConfigString { } object GenerateBootROM { - def apply(p: Parameters, address: BigInt) = { + def apply(p: Parameters, address: BigInt, configString: String) = { val romdata = Files.readAllBytes(Paths.get(p(BootROMFile))) val rom = ByteBuffer.wrap(romdata) @@ -95,6 +95,6 @@ object GenerateBootROM { require(rom.getInt(12) == 0, "Config string address position should not be occupied by code") rom.putInt(12, configStringAddr) - rom.array() ++ (ConfigStringOutput.contents.get.getBytes.toSeq) + rom.array() ++ (configString.getBytes.toSeq) } }