riscv/rocket-chip
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coreplex: configString is a property of the RISCVPlatform

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This commit is contained in:
Wesley W. Terpstra
2016-11-21 16:11:16 -08:00
parent e8be365b5d
commit 3d644b943c
5 changed files with 25 additions and 28 deletions
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6
src/main/scala/rocketchip/ExampleTop.scala
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@ -11,7 +11,6 @@ import rocketchip._
/** Example Top with Periphery */
class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex)
with DirectConnection
with PeripheryBootROM
with PeripheryExtInterrupts
with PeripheryMasterAXI4Mem
with PeripheryMasterAXI4MMIO {
@ -19,18 +18,17 @@ class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Par
}
class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer)
with PeripheryBootROMBundle
with PeripheryExtInterruptsBundle
with PeripheryMasterAXI4MemBundle
with PeripheryMasterAXI4MMIOBundle
class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
with PeripheryBootROMModule
with PeripheryExtInterruptsModule
with PeripheryMasterAXI4MemModule
with PeripheryMasterAXI4MMIOModule
class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex)
with PeripheryBootROM
with PeripheryDTM
with PeripheryCounter
with HardwiredResetVector {
@ -38,11 +36,13 @@ class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implic
}
class ExampleRocketTopBundle[+L <: ExampleRocketTop[DefaultCoreplex]](_outer: L) extends ExampleTopBundle(_outer)
with PeripheryBootROMBundle
with PeripheryDTMBundle
with PeripheryCounterBundle
with HardwiredResetVectorBundle
class ExampleRocketTopModule[+L <: ExampleRocketTop[DefaultCoreplex], +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
with PeripheryBootROMModule
with PeripheryDTMModule
with PeripheryCounterModule
with HardwiredResetVectorModule

8
src/main/scala/rocketchip/Periphery.scala
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@ -156,10 +156,12 @@ trait PeripheryMasterAXI4MMIOModule {
trait PeripheryBootROM {
this: TopNetwork =>
val coreplex: CoreplexRISCVPlatform
val bootrom_address = 0x1000
val bootrom_size = 0x1000
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, GenerateBootROM(p, bootrom_address), true, peripheryBusConfig.beatBytes))
private val bootrom_address = 0x1000
private val bootrom_size = 0x1000
private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.configString)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
}

4
src/main/scala/rocketchip/Utils.scala
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@ -84,7 +84,7 @@ object GenerateConfigString {
}
object GenerateBootROM {
def apply(p: Parameters, address: BigInt) = {
def apply(p: Parameters, address: BigInt, configString: String) = {
val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
val rom = ByteBuffer.wrap(romdata)
@ -95,6 +95,6 @@ object GenerateBootROM {
require(rom.getInt(12) == 0,
"Config string address position should not be occupied by code")
rom.putInt(12, configStringAddr)
rom.array() ++ (ConfigStringOutput.contents.get.getBytes.toSeq)
rom.array() ++ (configString.getBytes.toSeq)
}
}