TileLinkIO.GrantAck -> TileLinkIO.Finish
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Subproject commit 1a921d1760d7861ae60a67b659ec022a79740559
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Subproject commit 23a104b04472df241ca3074d0adf45c93d3da223
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@ -200,7 +200,7 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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case ((outer, client), i) =>
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case ((outer, client), i) =>
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
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outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.grant_ack, i))
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i))
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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client.probe <> Queue(outer.probe)
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}
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}
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@ -64,7 +64,7 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo
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case ((outer, client), i) =>
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case ((outer, client), i) =>
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
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outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
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outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
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outer.grant_ack <> Queue(TileLinkHeaderOverwriter(client.grant_ack, i))
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outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i))
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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client.probe <> Queue(outer.probe)
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}
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}
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@ -76,18 +76,17 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo
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import MemoryConstants._
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import MemoryConstants._
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import TileLinkSizeConstants._
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import TileLinkSizeConstants._
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class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extends Module {
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import MemoryConstants._
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val io = new Bundle {
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val host_in = new DecoupledIO(new HostPacket(htif_width)).flip()
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class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf)
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val host_out = new DecoupledIO(new HostPacket(htif_width))
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val host_clk = Bool(OUTPUT)
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class FPGATop extends Module {
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val host_clk_edge = Bool(OUTPUT)
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val htif_width = 16
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val host_debug_stats_pcr = Bool(OUTPUT)
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val mem_req_cmd = new DecoupledIO(new MemReqCmd())
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val mem_req_data = new DecoupledIO(new MemData())
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val mem_resp = (new DecoupledIO(new MemResp())).flip()
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}
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4)
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val io = new FPGATopIO(htif_width)
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val co = new MESICoherence
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val co = new MESICoherence
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val ntiles = 1
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val ntiles = 1
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val nbanks = 1
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val nbanks = 1
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@ -131,94 +130,9 @@ class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extend
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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}
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}
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io.host_in.ready := uncore.io.host.in.ready
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uncore.io.host <> io.host
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uncore.io.host.in.bits := io.host_in.bits.data
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uncore.io.mem <> io.mem
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uncore.io.host.in.valid := io.host_in.valid
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uncore.io.host.out.ready := io.host_out.ready
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io.host_out.bits.data := uncore.io.host.out.bits
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io.host_out.valid := uncore.io.host.out.valid
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io.host_clk := uncore.io.host.clk
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io.host_clk_edge := uncore.io.host.clk_edge
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io.host_debug_stats_pcr := uncore.io.host.debug_stats_pcr
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io.mem_req_cmd <> uncore.io.mem.req_cmd
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io.mem_req_data <> uncore.io.mem.req_data
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io.mem_resp <> uncore.io.mem.resp
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}
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import MemoryConstants._
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class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf)
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class FPGATop extends Module {
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val htif_width = 16
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4)
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val deviceWidth = ROW_WIDTH/mif.dataBits
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implicit val mc = MemoryControllerConfiguration(deviceWidth, (if(deviceWidth == 4) 0 else log2Up(deviceWidth/4)), mif)
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val io = new FPGATopIO(htif_width)
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val referenceChip = Module(new Fame1Wrapper(new ReferenceChip(htif_width)))
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val dramModel = Module(new DRAMSystemWrapper())
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//dram model parameters setup
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dramModel.io.params.tRAS := UInt(4)
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dramModel.io.params.tRCD := UInt(4)
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dramModel.io.params.tRP := UInt(4)
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dramModel.io.params.tCCD := UInt(4)
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dramModel.io.params.tRTP := UInt(4)
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dramModel.io.params.tWTR := UInt(4)
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dramModel.io.params.tWR := UInt(4)
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dramModel.io.params.tRRD := UInt(4)
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//host to reference chip connections
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referenceChip.DecoupledIOs("host_in").host_valid := Bool(true)
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referenceChip.DecoupledIOs("host_in").target.bits := io.host.in.bits
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referenceChip.DecoupledIOs("host_in").target.valid := io.host.in.valid
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io.host.in.ready := referenceChip.DecoupledIOs("host_in").host_ready && referenceChip.DecoupledIOs("host_in").target.ready
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io.host.out.valid := referenceChip.DecoupledIOs("host_out").host_valid && referenceChip.DecoupledIOs("host_out").target.valid
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io.host.out.bits := referenceChip.DecoupledIOs("host_out").target.bits
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referenceChip.DecoupledIOs("host_out").target.ready := io.host.out.ready
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referenceChip.DecoupledIOs("host_out").host_ready := Bool(true)
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io.host.clk := referenceChip.DebugIOs("host_clk").toBits()(0)
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io.host.clk_edge := referenceChip.DebugIOs("host_clk_edge").toBits()(0)
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io.host.debug_stats_pcr := referenceChip.DebugIOs("host_debug_stats_pcr").toBits()(0)
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//reference chip to dram model connections
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val mem_req_cmd_queue = Module(new FameQueue(8)(new MemReqCmd()))
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val mem_req_data_queue = Module(new FameQueue(8)(new MemData()))
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val mem_resp_queue = Module(new FameQueue(8)(new MemResp()))
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//cmd queue
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FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_req_cmd"), mem_req_cmd_queue.io.enq, new MemReqCmd)
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mem_req_cmd_queue.io.deq <> dramModel.io.memReqCmd
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//data queue
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FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_req_data"), mem_req_data_queue.io.enq, new MemData)
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mem_req_data_queue.io.deq <> dramModel.io.memReqData
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//resp queue
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mem_resp_queue.io.enq <> dramModel.io.memResp
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FameDecoupledIO.connect(referenceChip.DecoupledIOs("mem_resp"), mem_resp_queue.io.deq, new MemResp)
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//dram model to outside memory connections
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val host_mem_cmd_queue = Module(new Queue(new MemReqCmd, 2))
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val host_mem_data_queue = Module(new Queue(new MemData, mif.dataBeats))
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val host_mem_resp_queue = Module(new Queue(new MemResp, mif.dataBeats))
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host_mem_cmd_queue.io.enq <> dramModel.io.mem.req_cmd
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host_mem_cmd_queue.io.deq <> io.mem.req_cmd
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host_mem_data_queue.io.enq <> dramModel.io.mem.req_data
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host_mem_data_queue.io.deq <> io.mem.req_data
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host_mem_resp_queue.io.enq <> io.mem.resp
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host_mem_resp_queue.io.deq <> dramModel.io.mem.resp
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}
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}
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abstract class AXISlave extends Module {
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abstract class AXISlave extends Module {
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@ -36,7 +36,7 @@ class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends L
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val relNet = Module(new BasicCrossbar(new Release))
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val relNet = Module(new BasicCrossbar(new Release))
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val prbNet = Module(new BasicCrossbar(new Probe))
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val prbNet = Module(new BasicCrossbar(new Probe))
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val gntNet = Module(new BasicCrossbar(new Grant))
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val gntNet = Module(new BasicCrossbar(new Grant))
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val ackNet = Module(new BasicCrossbar(new GrantAck))
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val ackNet = Module(new BasicCrossbar(new Finish))
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// Aliases for the various network IO bundle types
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// Aliases for the various network IO bundle types
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type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
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type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
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@ -125,5 +125,5 @@ class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends L
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doFIFOHookups(relNet.io, (tl: TileLinkIO) => tl.release)
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doFIFOHookups(relNet.io, (tl: TileLinkIO) => tl.release)
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doFIFOHookups(prbNet.io, (tl: TileLinkIO) => tl.probe)
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doFIFOHookups(prbNet.io, (tl: TileLinkIO) => tl.probe)
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doFIFOHookups(gntNet.io, (tl: TileLinkIO) => tl.grant)
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doFIFOHookups(gntNet.io, (tl: TileLinkIO) => tl.grant)
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doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.grant_ack)
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doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.finish)
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}
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}
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2
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2
uncore
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Subproject commit f6a4cb6ecfc1854d5100aed72bcb7978ea025c13
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Subproject commit 4ca76ebaad5e796121fcb6843b00a6e5da25cd6f
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