riscv/rocket-chip
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new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels

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This commit is contained in:
Henry Cook
2017-04-27 15:22:52 -07:00
committed by Andrew Waterman
parent bdb526a9f0
commit 3d0ed80ef6
6 changed files with 32 additions and 26 deletions
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7
src/main/scala/tile/Core.scala
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@ -77,11 +77,10 @@ abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundl
trait HasCoreIO extends HasTileParameters {
implicit val p: Parameters
val io = new Bundle {
val io = new CoreBundle()(p) with HasExternallyDrivenTileConstants {
val interrupts = new TileInterrupts().asInput
val hartid = UInt(INPUT, hartIdLen)
val imem = new FrontendIO()(p)
val dmem = new HellaCacheIO()(p)
val imem = new FrontendIO
val dmem = new HellaCacheIO
val ptw = new DatapathPTWIO().flip
val fpu = new FPUCoreIO().flip
val rocc = new RoCCCoreIO().flip