From 3d0ed80ef6eac67938f831b46295a783439d3334 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 27 Apr 2017 15:22:52 -0700 Subject: [PATCH] new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels --- src/main/scala/coreplex/Configs.scala | 3 +++ src/main/scala/coreplex/RISCVPlatform.scala | 9 ++++---- src/main/scala/rocket/HellaCache.scala | 4 ++-- src/main/scala/rocket/Tile.scala | 12 +++-------- src/main/scala/tile/BaseTile.scala | 23 ++++++++++++++------- src/main/scala/tile/Core.scala | 7 +++---- 6 files changed, 32 insertions(+), 26 deletions(-) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index a5ccc232..3a72cb94 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -19,6 +19,9 @@ class BaseCoreplexConfig extends Config ((site, here, up) => { case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */ case ASIdBits => 0 case XLen => 64 // Applies to all cores + case ResetVectorBits => site(PAddrBits) + case MaxHartIdBits => log2Up(site(NTiles)) + case MaxPriorityLevels => 7 case BuildCore => (p: Parameters) => new Rocket()(p) case RocketCrossing => SynchronousCrossing() case RocketTilesKey => Nil diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala index 1a8850b8..ec65c192 100644 --- a/src/main/scala/coreplex/RISCVPlatform.scala +++ b/src/main/scala/coreplex/RISCVPlatform.scala @@ -3,19 +3,20 @@ package coreplex import Chisel._ -import config._ -import junctions._ +import config.Field import diplomacy._ import tile._ import uncore.tilelink2._ import uncore.devices._ import util._ +case object MaxPriorityLevels extends Field[Int] + trait CoreplexRISCVPlatform extends CoreplexNetwork { val module: CoreplexRISCVPlatformModule val debug = LazyModule(new TLDebugModule()) - val plic = LazyModule(new TLPLIC(maxPriorities = 7)) + val plic = LazyModule(new TLPLIC(maxPriorities = p(MaxPriorityLevels))) val clint = LazyModule(new CoreplexLocalInterrupter) debug.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) @@ -34,7 +35,7 @@ trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle { val debug = new ClockedDMIIO().flip val rtcToggle = Bool(INPUT) - val resetVector = UInt(INPUT, p(XLen)) + val resetVector = UInt(INPUT, p(ResetVectorBits)) val ndreset = Bool(OUTPUT) val dmactive = Bool(OUTPUT) } diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index f019636d..c14cf0b4 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -184,12 +184,12 @@ object HellaCache { /** Mix-ins for constructing tiles that have a HellaCache */ -trait HasHellaCache extends HasTileLinkMasterPort { +trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters { val module: HasHellaCacheModule implicit val p: Parameters def findScratchpadFromICache: Option[AddressSet] var nDCachePorts = 0 - val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _) + val dcache = HellaCache(usingBlockingDCache, findScratchpadFromICache _) masterNode := dcache.node } diff --git a/src/main/scala/rocket/Tile.scala b/src/main/scala/rocket/Tile.scala index c92060bf..8691d9a3 100644 --- a/src/main/scala/rocket/Tile.scala +++ b/src/main/scala/rocket/Tile.scala @@ -176,12 +176,10 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) xing.intnode := intNode lazy val module = new LazyModuleImp(this) { - val io = new CoreBundle { + val io = new CoreBundle with HasExternallyDrivenTileConstants { val master = masterNode.bundleOut val slave = slaveNode.bundleIn val interrupts = intNode.bundleIn - val hartid = UInt(INPUT, hartIdLen) - val resetVector = UInt(INPUT, p(XLen)) } // signals that do not change: rocket.module.io.hartid := io.hartid @@ -208,12 +206,10 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters xing.intnode := intNode lazy val module = new LazyModuleImp(this) { - val io = new CoreBundle { + val io = new CoreBundle with HasExternallyDrivenTileConstants { val master = masterNode.bundleOut val slave = slaveNode.bundleIn val interrupts = intNode.bundleIn - val hartid = UInt(INPUT, hartIdLen) - val resetVector = UInt(INPUT, p(XLen)) } // signals that do not change: rocket.module.io.hartid := io.hartid @@ -244,12 +240,10 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet xing.intnode := intNode lazy val module = new LazyModuleImp(this) { - val io = new CoreBundle { + val io = new CoreBundle with HasExternallyDrivenTileConstants { val master = masterNode.bundleOut val slave = slaveNode.bundleIn val interrupts = intNode.bundleIn - val hartid = UInt(INPUT, hartIdLen) - val resetVector = UInt(INPUT, p(XLen)) } // signals that do not change: rocket.module.io.hartid := io.hartid diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 9ab20300..ad10d2d6 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -11,6 +11,8 @@ import util._ case object SharedMemoryTLEdge extends Field[TLEdgeOut] case object TileKey extends Field[TileParams] +case object ResetVectorBits extends Field[Int] +case object MaxHartIdBits extends Field[Int] trait TileParams { val core: CoreParams @@ -30,8 +32,9 @@ trait HasTileParameters { val usingRoCC = !tileParams.rocc.isEmpty val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0 val usingPTW = usingVM + val usingBlockingDCache = tileParams.dcache.get.nMSHRs == 0 val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined - val hartIdLen = log2Up(p(uncore.devices.NTiles)) + val hartIdLen = p(MaxHartIdBits) def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size } @@ -48,8 +51,8 @@ abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L val io = _io () } -// Uses TileLink master port to connect caches and accelerators to the coreplex -trait HasTileLinkMasterPort extends HasTileParameters { +/** Uses TileLink master port to connect caches and accelerators to the coreplex */ +trait HasTileLinkMasterPort { implicit val p: Parameters val module: HasTileLinkMasterPortModule val masterNode = TLOutputNode() @@ -65,6 +68,14 @@ trait HasTileLinkMasterPortModule { val io: HasTileLinkMasterPortBundle } +/** Some other standard inputs */ +trait HasExternallyDrivenTileConstants extends Bundle { + implicit val p: Parameters + val hartid = UInt(INPUT, p(MaxHartIdBits)) + val resetVector = UInt(INPUT, p(ResetVectorBits)) +} + +/** Base class for all Tiles that use TileLink */ abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile with HasTileLinkMasterPort with HasExternalInterrupts { @@ -74,10 +85,8 @@ abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer) with HasTileParameters with HasTileLinkMasterPortBundle - with HasExternalInterruptsBundle { - val hartid = UInt(INPUT, hartIdLen) - val resetVector = UInt(INPUT, p(XLen)) -} + with HasExternalInterruptsBundle + with HasExternallyDrivenTileConstants class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io) with HasTileLinkMasterPortModule diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala index 23158fa9..2befafad 100644 --- a/src/main/scala/tile/Core.scala +++ b/src/main/scala/tile/Core.scala @@ -77,11 +77,10 @@ abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundl trait HasCoreIO extends HasTileParameters { implicit val p: Parameters - val io = new Bundle { + val io = new CoreBundle()(p) with HasExternallyDrivenTileConstants { val interrupts = new TileInterrupts().asInput - val hartid = UInt(INPUT, hartIdLen) - val imem = new FrontendIO()(p) - val dmem = new HellaCacheIO()(p) + val imem = new FrontendIO + val dmem = new HellaCacheIO val ptw = new DatapathPTWIO().flip val fpu = new FPUCoreIO().flip val rocc = new RoCCCoreIO().flip