new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels

src/main/scala/tile/BaseTile.scala

@@ -11,6 +11,8 @@ import util._
 
 case object SharedMemoryTLEdge extends Field[TLEdgeOut]
 case object TileKey extends Field[TileParams]
+case object ResetVectorBits extends Field[Int]
+case object MaxHartIdBits extends Field[Int]
 
 trait TileParams {
   val core: CoreParams
@@ -30,8 +32,9 @@ trait HasTileParameters {
   val usingRoCC = !tileParams.rocc.isEmpty
   val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
   val usingPTW = usingVM
+  val usingBlockingDCache = tileParams.dcache.get.nMSHRs == 0
   val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
-  val hartIdLen = log2Up(p(uncore.devices.NTiles))
+  val hartIdLen = p(MaxHartIdBits)
 
   def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
 }
@@ -48,8 +51,8 @@ abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L
   val io = _io ()
 }
 
-// Uses TileLink master port to connect caches and accelerators to the coreplex
-trait HasTileLinkMasterPort extends HasTileParameters {
+/** Uses TileLink master port to connect caches and accelerators to the coreplex */
+trait HasTileLinkMasterPort {
   implicit val p: Parameters
   val module: HasTileLinkMasterPortModule
   val masterNode = TLOutputNode()
@@ -65,6 +68,14 @@ trait HasTileLinkMasterPortModule {
   val io: HasTileLinkMasterPortBundle
 }
 
+/** Some other standard inputs */
+trait HasExternallyDrivenTileConstants extends Bundle {
+  implicit val p: Parameters
+  val hartid = UInt(INPUT, p(MaxHartIdBits))
+  val resetVector = UInt(INPUT, p(ResetVectorBits))
+}
+
+/** Base class for all Tiles that use TileLink */
 abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
     with HasTileLinkMasterPort
     with HasExternalInterrupts {
@@ -74,10 +85,8 @@ abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends
 class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
     with HasTileParameters
     with HasTileLinkMasterPortBundle
-    with HasExternalInterruptsBundle {
-  val hartid = UInt(INPUT, hartIdLen)
-  val resetVector = UInt(INPUT, p(XLen))
-}
+    with HasExternalInterruptsBundle
+    with HasExternallyDrivenTileConstants
 
 class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
     with HasTileLinkMasterPortModule