riscv/rocket-chip
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new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels

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This commit is contained in:
Henry Cook
2017-04-27 15:22:52 -07:00
committed by Andrew Waterman
parent bdb526a9f0
commit 3d0ed80ef6
6 changed files with 32 additions and 26 deletions
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4
src/main/scala/rocket/HellaCache.scala
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@ -184,12 +184,12 @@ object HellaCache {
/** Mix-ins for constructing tiles that have a HellaCache */
trait HasHellaCache extends HasTileLinkMasterPort {
trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
val module: HasHellaCacheModule
implicit val p: Parameters
def findScratchpadFromICache: Option[AddressSet]
var nDCachePorts = 0
val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
val dcache = HellaCache(usingBlockingDCache, findScratchpadFromICache _)
masterNode := dcache.node
}

12
src/main/scala/rocket/Tile.scala
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@ -176,12 +176,10 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
xing.intnode := intNode
lazy val module = new LazyModuleImp(this) {
val io = new CoreBundle {
val io = new CoreBundle with HasExternallyDrivenTileConstants {
val master = masterNode.bundleOut
val slave = slaveNode.bundleIn
val interrupts = intNode.bundleIn
val hartid = UInt(INPUT, hartIdLen)
val resetVector = UInt(INPUT, p(XLen))
}
// signals that do not change:
rocket.module.io.hartid := io.hartid
@ -208,12 +206,10 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
xing.intnode := intNode
lazy val module = new LazyModuleImp(this) {
val io = new CoreBundle {
val io = new CoreBundle with HasExternallyDrivenTileConstants {
val master = masterNode.bundleOut
val slave = slaveNode.bundleIn
val interrupts = intNode.bundleIn
val hartid = UInt(INPUT, hartIdLen)
val resetVector = UInt(INPUT, p(XLen))
}
// signals that do not change:
rocket.module.io.hartid := io.hartid
@ -244,12 +240,10 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
xing.intnode := intNode
lazy val module = new LazyModuleImp(this) {
val io = new CoreBundle {
val io = new CoreBundle with HasExternallyDrivenTileConstants {
val master = masterNode.bundleOut
val slave = slaveNode.bundleIn
val interrupts = intNode.bundleIn
val hartid = UInt(INPUT, hartIdLen)
val resetVector = UInt(INPUT, p(XLen))
}
// signals that do not change:
rocket.module.io.hartid := io.hartid