riscv/rocket-chip
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new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels

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This commit is contained in:
Henry Cook
2017-04-27 15:22:52 -07:00
committed by Andrew Waterman
parent bdb526a9f0
commit 3d0ed80ef6
6 changed files with 32 additions and 26 deletions
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3
src/main/scala/coreplex/Configs.scala
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@ -19,6 +19,9 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case ASIdBits => 0
case XLen => 64 // Applies to all cores
case ResetVectorBits => site(PAddrBits)
case MaxHartIdBits => log2Up(site(NTiles))
case MaxPriorityLevels => 7
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketCrossing => SynchronousCrossing()
case RocketTilesKey => Nil

9
src/main/scala/coreplex/RISCVPlatform.scala
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@ -3,19 +3,20 @@
package coreplex
import Chisel._
import config._
import junctions._
import config.Field
import diplomacy._
import tile._
import uncore.tilelink2._
import uncore.devices._
import util._
case object MaxPriorityLevels extends Field[Int]
trait CoreplexRISCVPlatform extends CoreplexNetwork {
val module: CoreplexRISCVPlatformModule
val debug = LazyModule(new TLDebugModule())
val plic = LazyModule(new TLPLIC(maxPriorities = 7))
val plic = LazyModule(new TLPLIC(maxPriorities = p(MaxPriorityLevels)))
val clint = LazyModule(new CoreplexLocalInterrupter)
debug.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
@ -34,7 +35,7 @@ trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle {
val debug = new ClockedDMIIO().flip
val rtcToggle = Bool(INPUT)
val resetVector = UInt(INPUT, p(XLen))
val resetVector = UInt(INPUT, p(ResetVectorBits))
val ndreset = Bool(OUTPUT)
val dmactive = Bool(OUTPUT)
}