riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

pending read fix

Browse Source
This commit is contained in:
Henry Cook 2015-03-18 22:41:09 -07:00
parent 004ad11af6
commit 3cf033180f
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
uncore/src/main/scala/cache.scala
View File

@ -826,9 +826,10 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
pending_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType), pending_puts := Mux(io.iacq().isBuiltInType(Acquire.putBlockType),
dropPendingBitWhenHasData(io.inner.acquire), dropPendingBitWhenHasData(io.inner.acquire),
UInt(0)) UInt(0))
pending_reads := Mux(io.iacq().isBuiltInType(), pending_reads := Mux(io.iacq().isBuiltInType(Acquire.getBlockType) ||
addPendingBitWhenGetOrAtomic(io.inner.acquire), !io.iacq().isBuiltInType(),
SInt(-1, width = innerDataBeats)).toUInt SInt(-1, width = innerDataBeats),
addPendingBitWhenGetOrAtomic(io.inner.acquire)).toUInt
pending_writes := addPendingBitWhenHasData(io.inner.acquire) pending_writes := addPendingBitWhenHasData(io.inner.acquire)
pending_resps := UInt(0) pending_resps := UInt(0)
pending_ignt_data := UInt(0) pending_ignt_data := UInt(0)