riscv/rocket-chip
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don't make HTIF clock divider tied to backup memory

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This commit is contained in:
Howard Mao 2016-03-09 13:56:50 -08:00
parent 5e145515e1
commit 3c9e63f5a5
2 changed files with 11 additions and 4 deletions
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5
src/main/scala/Configs.scala
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@ -228,7 +228,8 @@ class DefaultConfig extends Config (
case BankIdLSB => 0
case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
case UseBackupMemoryPort => true
case UseBackupMemoryPort => false
case UseHtifClockDiv => true
case MMIOBase => Dump("MEM_SIZE", BigInt(1L << 30)) // 1 GB
case DeviceTree => makeDeviceTree()
case GlobalAddrMap => {
@ -356,7 +357,7 @@ class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
class FPGAConfig extends Config (
(pname,site,here) => pname match {
case NAcquireTransactors => 4
case UseBackupMemoryPort => false
case UseHtifClockDiv => false
}
)

10
src/main/scala/RocketChip.scala
View File

@ -27,6 +27,8 @@ case object BankIdLSB extends Field[Int]
case object NOutstandingMemReqsPerChannel extends Field[Int]
/** Whether to use the slow backup memory port [VLSI] */
case object UseBackupMemoryPort extends Field[Boolean]
/** Whether to divide HTIF clock */
case object UseHtifClockDiv extends Field[Boolean]
/** Function for building some kind of coherence manager agent */
case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
/** Function for building some kind of tile connected to a reset signal */
@ -120,6 +122,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
io.host <> uncore.io.host
if (p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
else { uncore.io.mem_backup_ctrl.en := Bool(false) }
io.mem.zip(uncore.io.mem).foreach { case (outer, inner) =>
TopUtils.connectNasti(outer, inner)
@ -189,7 +192,7 @@ class Uncore(implicit val p: Parameters) extends Module
// Wire the htif to the memory port(s) and host interface
io.host.debug_stats_csr := htif.io.host.debug_stats_csr
io.mem <> outmemsys.io.mem
if(p(UseBackupMemoryPort)) {
if(p(UseHtifClockDiv)) {
outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
@ -344,5 +347,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
"Backup memory port only works when 1 memory channel is enabled")
require(channelConfigs.sortWith(_ < _)(0) == 1,
"Backup memory port requires a single memory port mux config")
} else { io.mem <> mem_channels }
} else {
io.mem <> mem_channels
io.mem_backup.req.valid := Bool(false)
}
}