riscv/rocket-chip
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don't make HTIF clock divider tied to backup memory

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Howard Mao
2016-03-09 13:56:50 -08:00
parent 5e145515e1
commit 3c9e63f5a5
2 changed files with 11 additions and 4 deletions
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5
src/main/scala/Configs.scala
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@ -228,7 +228,8 @@ class DefaultConfig extends Config (
case BankIdLSB => 0
case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
case UseBackupMemoryPort => true
case UseBackupMemoryPort => false
case UseHtifClockDiv => true
case MMIOBase => Dump("MEM_SIZE", BigInt(1L << 30)) // 1 GB
case DeviceTree => makeDeviceTree()
case GlobalAddrMap => {
@ -356,7 +357,7 @@ class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
class FPGAConfig extends Config (
(pname,site,here) => pname match {
case NAcquireTransactors => 4
case UseBackupMemoryPort => false
case UseHtifClockDiv => false
}
)