riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Add exception signal to rocc interface

Browse Source
This commit is contained in:
Stephen Twigg 2014-01-28 22:13:16 -08:00
parent 30b894c2c4
commit 3c3c469725
2 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
rocket/src/main/scala/ctrl.scala
View File

@ -738,4 +738,5 @@ class Control(implicit conf: RocketConfiguration) extends Module
io.dmem.req.bits.phys := Bool(false)
io.rocc.cmd.valid := wb_rocc_val
io.rocc.exception := wb_reg_xcpt && sr.er
}

7
rocket/src/main/scala/rocc.scala
View File

@ -38,14 +38,17 @@ class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
val cmd = Decoupled(new RoCCCommand).flip
val resp = Decoupled(new RoCCResponse)
val mem = new HellaCacheIO()(conf.dcache)
val busy = Bool(OUTPUT)
val interrupt = Bool(OUTPUT)
// These should be handled differently, eventually
val imem = new UncachedTileLinkIO()(conf.tl)
val iptw = new TLBPTWIO
val dptw = new TLBPTWIO
val pptw = new TLBPTWIO
val cp_dfma = new ioFMA(65).flip
val cp_sfma = new ioFMA(33).flip
val busy = Bool(OUTPUT)
val interrupt = Bool(OUTPUT)
val exception = Bool(INPUT)
override def clone = new RoCCInterface().asInstanceOf[this.type]
}