diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index f7f41a94..97525f0b 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -738,4 +738,5 @@ class Control(implicit conf: RocketConfiguration) extends Module
   io.dmem.req.bits.phys := Bool(false)
 
   io.rocc.cmd.valid := wb_rocc_val
+  io.rocc.exception := wb_reg_xcpt && sr.er
 }
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index 31cd572f..aa099d00 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -38,14 +38,17 @@ class RoCCInterface(implicit conf: RocketConfiguration) extends Bundle
   val cmd = Decoupled(new RoCCCommand).flip
   val resp = Decoupled(new RoCCResponse)
   val mem = new HellaCacheIO()(conf.dcache)
+  val busy = Bool(OUTPUT)
+  val interrupt = Bool(OUTPUT)
+  
+  // These should be handled differently, eventually
   val imem = new UncachedTileLinkIO()(conf.tl)
   val iptw = new TLBPTWIO
   val dptw = new TLBPTWIO
   val pptw = new TLBPTWIO
   val cp_dfma = new ioFMA(65).flip
   val cp_sfma = new ioFMA(33).flip
-  val busy = Bool(OUTPUT)
-  val interrupt = Bool(OUTPUT)
+  val exception = Bool(INPUT)
 
   override def clone = new RoCCInterface().asInstanceOf[this.type]
 }