riscv/rocket-chip
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Chisel3 <> reverse fix

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This commit is contained in:
Palmer Dabbelt 2016-02-05 09:56:42 -08:00
parent c944193e16
commit 3bb0f11e6c
1 changed files with 1 additions and 1 deletions
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src/main/scala/Vlsi.scala
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@ -11,7 +11,7 @@ class MemDessert(topParams: Parameters) extends Module {
implicit val p = topParams implicit val p = topParams
val io = new MemDesserIO(p(HtifKey).width) val io = new MemDesserIO(p(HtifKey).width)
val x = Module(new MemDesser(p(HtifKey).width)) val x = Module(new MemDesser(p(HtifKey).width))
io.narrow <> x.io.narrow x.io.narrow <> io.narrow
io.wide <> x.io.wide io.wide <> x.io.wide
} }