From 3bb0f11e6ce670b77a0e347ec06d71087bc1e5ea Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 5 Feb 2016 09:56:42 -0800 Subject: [PATCH] Chisel3 <> reverse fix --- src/main/scala/Vlsi.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/Vlsi.scala b/src/main/scala/Vlsi.scala index 4f9a42aa..bb4f6f5c 100644 --- a/src/main/scala/Vlsi.scala +++ b/src/main/scala/Vlsi.scala @@ -11,7 +11,7 @@ class MemDessert(topParams: Parameters) extends Module { implicit val p = topParams val io = new MemDesserIO(p(HtifKey).width) val x = Module(new MemDesser(p(HtifKey).width)) - io.narrow <> x.io.narrow + x.io.narrow <> io.narrow io.wide <> x.io.wide }