riscv/rocket-chip
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debug: correctly declare reg_debugint

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This commit is contained in:
Megan Wachs
2017-06-27 13:38:02 -07:00
parent 56839b2c62
commit 3b9550ede3
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/rocket/CSR.scala
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@@ -212,6 +212,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
reset_dcsr.xdebugver := 1
reset_dcsr.prv := PRV.M
val reg_dcsr = Reg(init=reset_dcsr)
val reg_debugint = RegInit(Bool(false), next = io.interrupts.debug)
val (supported_interrupts, delegable_interrupts) = {
val sup = Wire(new MIP)
@@ -719,7 +720,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
reg_mip.mtip := io.interrupts.mtip
reg_mip.msip := io.interrupts.msip
reg_mip.meip := io.interrupts.meip
reg_debugint := RegInit(Bool(false), next = io.interrupts.debug)
if (!usingVM) {
reg_mideleg := 0