diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index 377eb427..e90e92ca 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -212,6 +212,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
   reset_dcsr.xdebugver := 1
   reset_dcsr.prv := PRV.M
   val reg_dcsr = Reg(init=reset_dcsr)
+  val reg_debugint = RegInit(Bool(false), next = io.interrupts.debug)
 
   val (supported_interrupts, delegable_interrupts) = {
     val sup = Wire(new MIP)
@@ -719,7 +720,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
   reg_mip.mtip := io.interrupts.mtip
   reg_mip.msip := io.interrupts.msip
   reg_mip.meip := io.interrupts.meip
-  reg_debugint := RegInit(Bool(false), next = io.interrupts.debug)
 
   if (!usingVM) {
     reg_mideleg := 0