riscv/rocket-chip
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final Reg changes

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This commit is contained in:
Henry Cook
2013-08-15 15:28:15 -07:00
parent b570435847
commit 3a266cbbfa
16 changed files with 117 additions and 117 deletions
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4
rocket/src/main/scala/util.scala
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@ -117,12 +117,12 @@ case class WideCounter(width: Int, inc: Bool = Bool(true))
{
private val isWide = width >= 4
private val smallWidth = if (isWide) log2Up(width) else width
private val small = RegReset(UInt(0, smallWidth))
private val small = Reg(init=UInt(0, smallWidth))
private val nextSmall = small + UInt(1, smallWidth+1)
when (inc) { small := nextSmall(smallWidth-1,0) }
private val large = if (isWide) {
val r = RegReset(UInt(0, width - smallWidth))
val r = Reg(init=UInt(0, width - smallWidth))
when (inc && nextSmall(smallWidth)) { r := r + UInt(1) }
r
} else null