From 3a266cbbfaa6a60d73b0c2f50347ce2d43ae62d5 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 15 Aug 2013 15:28:15 -0700 Subject: [PATCH] final Reg changes --- rocket/src/main/scala/arbiter.scala | 2 +- rocket/src/main/scala/core.scala | 2 +- rocket/src/main/scala/ctrl.scala | 98 +++++++++++++------------- rocket/src/main/scala/ctrl_vec.scala | 2 +- rocket/src/main/scala/divider.scala | 4 +- rocket/src/main/scala/dpath.scala | 2 +- rocket/src/main/scala/dpath_util.scala | 16 ++--- rocket/src/main/scala/dpath_vec.scala | 10 +-- rocket/src/main/scala/fpu.scala | 20 +++--- rocket/src/main/scala/htif.scala | 14 ++-- rocket/src/main/scala/icache.scala | 16 ++--- rocket/src/main/scala/multiplier.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 36 +++++----- rocket/src/main/scala/ptw.scala | 2 +- rocket/src/main/scala/tlb.scala | 4 +- rocket/src/main/scala/util.scala | 4 +- 16 files changed, 117 insertions(+), 117 deletions(-) diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala index 78c3b47e..3ad0e750 100644 --- a/rocket/src/main/scala/arbiter.scala +++ b/rocket/src/main/scala/arbiter.scala @@ -10,7 +10,7 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Modu val mem = new HellaCacheIO()(conf.dcache) } - val r_valid = io.requestor.map(r => RegUpdate(r.req.valid)) + val r_valid = io.requestor.map(r => Reg(next=r.req.valid)) io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_) io.requestor(0).req.ready := io.mem.req.ready diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala index f0872dcc..788e18dc 100644 --- a/rocket/src/main/scala/core.scala +++ b/rocket/src/main/scala/core.scala @@ -42,7 +42,7 @@ class Core(implicit conf: RocketConfiguration) extends Module } else null if (conf.vec) { - val vu = Module(new vu(RegUpdate(reset))) + val vu = Module(new vu(Reg(next=reset))) val vdtlb = Module(new TLB(8)) ptw += vdtlb.io.ptw diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 20b59d9b..6831b144 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -355,59 +355,59 @@ class Control(implicit conf: RocketConfiguration) extends Module val id_waddr = Mux(id_sel_wa === WA_RA, RA, io.dpath.inst(31,27)); val id_load_use = Bool(); - val ex_reg_xcpt_interrupt = RegReset(Bool(false)) - val ex_reg_valid = RegReset(Bool(false)) - val ex_reg_eret = RegReset(Bool(false)) - val ex_reg_wen = RegReset(Bool(false)) - val ex_reg_fp_wen = RegReset(Bool(false)) - val ex_reg_flush_inst = RegReset(Bool(false)) - val ex_reg_jalr = RegReset(Bool(false)) - val ex_reg_btb_hit = RegReset(Bool(false)) - val ex_reg_div_mul_val = RegReset(Bool(false)) - val ex_reg_mem_val = RegReset(Bool(false)) - val ex_reg_xcpt = RegReset(Bool(false)) - val ex_reg_fp_val = RegReset(Bool(false)) - val ex_reg_vec_val = RegReset(Bool(false)) - val ex_reg_replay_next = RegReset(Bool(false)) - val ex_reg_load_use = RegReset(Bool(false)) - val ex_reg_pcr = RegReset(PCR.N) - val ex_reg_br_type = RegReset(BR_N) + val ex_reg_xcpt_interrupt = Reg(init=Bool(false)) + val ex_reg_valid = Reg(init=Bool(false)) + val ex_reg_eret = Reg(init=Bool(false)) + val ex_reg_wen = Reg(init=Bool(false)) + val ex_reg_fp_wen = Reg(init=Bool(false)) + val ex_reg_flush_inst = Reg(init=Bool(false)) + val ex_reg_jalr = Reg(init=Bool(false)) + val ex_reg_btb_hit = Reg(init=Bool(false)) + val ex_reg_div_mul_val = Reg(init=Bool(false)) + val ex_reg_mem_val = Reg(init=Bool(false)) + val ex_reg_xcpt = Reg(init=Bool(false)) + val ex_reg_fp_val = Reg(init=Bool(false)) + val ex_reg_vec_val = Reg(init=Bool(false)) + val ex_reg_replay_next = Reg(init=Bool(false)) + val ex_reg_load_use = Reg(init=Bool(false)) + val ex_reg_pcr = Reg(init=PCR.N) + val ex_reg_br_type = Reg(init=BR_N) val ex_reg_mem_cmd = Reg(Bits()) val ex_reg_mem_type = Reg(Bits()) val ex_reg_cause = Reg(UInt()) - val mem_reg_xcpt_interrupt = RegReset(Bool(false)) - val mem_reg_valid = RegReset(Bool(false)) - val mem_reg_eret = RegReset(Bool(false)) - val mem_reg_wen = RegReset(Bool(false)) - val mem_reg_fp_wen = RegReset(Bool(false)) - val mem_reg_flush_inst = RegReset(Bool(false)) - val mem_reg_div_mul_val = RegReset(Bool(false)) - val mem_reg_mem_val = RegReset(Bool(false)) - val mem_reg_xcpt = RegReset(Bool(false)) - val mem_reg_fp_val = RegReset(Bool(false)) - val mem_reg_vec_val = RegReset(Bool(false)) - val mem_reg_replay = RegReset(Bool(false)) - val mem_reg_replay_next = RegReset(Bool(false)) - val mem_reg_pcr = RegReset(PCR.N) + val mem_reg_xcpt_interrupt = Reg(init=Bool(false)) + val mem_reg_valid = Reg(init=Bool(false)) + val mem_reg_eret = Reg(init=Bool(false)) + val mem_reg_wen = Reg(init=Bool(false)) + val mem_reg_fp_wen = Reg(init=Bool(false)) + val mem_reg_flush_inst = Reg(init=Bool(false)) + val mem_reg_div_mul_val = Reg(init=Bool(false)) + val mem_reg_mem_val = Reg(init=Bool(false)) + val mem_reg_xcpt = Reg(init=Bool(false)) + val mem_reg_fp_val = Reg(init=Bool(false)) + val mem_reg_vec_val = Reg(init=Bool(false)) + val mem_reg_replay = Reg(init=Bool(false)) + val mem_reg_replay_next = Reg(init=Bool(false)) + val mem_reg_pcr = Reg(init=PCR.N) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) - val wb_reg_valid = RegReset(Bool(false)) - val wb_reg_pcr = RegReset(PCR.N) - val wb_reg_wen = RegReset(Bool(false)) - val wb_reg_fp_wen = RegReset(Bool(false)) - val wb_reg_flush_inst = RegReset(Bool(false)) - val wb_reg_mem_val = RegReset(Bool(false)) - val wb_reg_eret = RegReset(Bool(false)) - val wb_reg_xcpt = RegReset(Bool(false)) - val wb_reg_replay = RegReset(Bool(false)) + val wb_reg_valid = Reg(init=Bool(false)) + val wb_reg_pcr = Reg(init=PCR.N) + val wb_reg_wen = Reg(init=Bool(false)) + val wb_reg_fp_wen = Reg(init=Bool(false)) + val wb_reg_flush_inst = Reg(init=Bool(false)) + val wb_reg_mem_val = Reg(init=Bool(false)) + val wb_reg_eret = Reg(init=Bool(false)) + val wb_reg_xcpt = Reg(init=Bool(false)) + val wb_reg_replay = Reg(init=Bool(false)) val wb_reg_cause = Reg(UInt()) - val wb_reg_fp_val = RegReset(Bool(false)) - val wb_reg_div_mul_val = RegReset(Bool(false)) + val wb_reg_fp_val = Reg(init=Bool(false)) + val wb_reg_div_mul_val = Reg(init=Bool(false)) val take_pc = Bool() - val pc_taken = RegUpdate(take_pc, Bool(false)) + val pc_taken = Reg(next=take_pc, init=Bool(false)) val take_pc_wb = Bool() val ctrl_killd = Bool() val ctrl_killx = Bool() @@ -611,17 +611,17 @@ class Control(implicit conf: RocketConfiguration) extends Module class Scoreboard(n: Int) { - val r = RegReset(Bits(0, n)) - var next = r + val r = Reg(init=Bits(0, n)) + var _next = r var ens = Bool(false) def apply(addr: UInt) = r(addr) - def set(en: Bool, addr: UInt): Unit = update(en, next | mask(en, addr)) - def clear(en: Bool, addr: UInt): Unit = update(en, next & ~mask(en, addr)) + def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr)) + def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) private def mask(en: Bool, addr: UInt) = Mux(en, UInt(1) << addr, UInt(0)) private def update(en: Bool, update: UInt) = { - next = update + _next = update ens = ens || en - when (ens) { r := next } + when (ens) { r := _next } } } diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index 85ef702b..2fa4c6f9 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -261,7 +261,7 @@ class rocketCtrlVec extends Module io.iface.exception := io.exception && io.sr_ev - val reg_hold = RegReset(Bool(false)) + val reg_hold = Reg(init=Bool(false)) when (valid_common && dec.io.sigs.xcpthold) { reg_hold := Bool(true) } when (io.eret) { reg_hold := Bool(false) } diff --git a/rocket/src/main/scala/divider.scala b/rocket/src/main/scala/divider.scala index 08e35766..6c6f0242 100644 --- a/rocket/src/main/scala/divider.scala +++ b/rocket/src/main/scala/divider.scala @@ -10,7 +10,7 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: Rocke val mulw = (w+mulUnroll-1)/mulUnroll*mulUnroll val s_ready :: s_neg_inputs :: s_mul_busy :: s_div_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(7) { UInt() }; - val state = RegReset(s_ready) + val state = Reg(init=s_ready) val req = Reg(io.req.bits.clone) val count = Reg(UInt(width = log2Up(w+1))) @@ -120,7 +120,7 @@ class Divider(earlyOut: Boolean = false)(implicit conf: RocketConfiguration) ext val w = io.req.bits.in1.getWidth val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(6) { UInt() }; - val state = RegReset(s_ready) + val state = Reg(init=s_ready) val count = Reg(UInt(width = log2Up(w+1))) val divby0 = Reg(Bool()) diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index a22d0803..4e32be4c 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -50,7 +50,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module val wb_reg_inst = Reg(Bits()) val wb_reg_waddr = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) - val wb_reg_ll_wb = RegReset(Bool(false)) + val wb_reg_ll_wb = Reg(init=Bool(false)) val wb_wdata = Bits() val wb_reg_store_data = Reg(Bits()) val wb_reg_rs1 = Reg(Bits()) diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 7e193a35..40ae0e14 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -36,7 +36,7 @@ class rocketDpathBTB(entries: Int) extends Module for (i <- 0 until entries) { val tag = Reg(UInt()) - val valid = RegReset(Bool(false)) + val valid = Reg(init=Bool(false)) hits(i) := valid && tag === io.current_pc updates(i) := valid && tag === io.correct_pc @@ -145,19 +145,19 @@ class PCR(implicit conf: RocketConfiguration) extends Module val reg_count = WideCounter(32) val reg_compare = Reg(Bits(width = 32)) val reg_cause = Reg(Bits(width = io.cause.getWidth)) - val reg_tohost = RegReset(Bits(0, conf.xprlen)) - val reg_fromhost = RegReset(Bits(0, conf.xprlen)) + val reg_tohost = Reg(init=Bits(0, conf.xprlen)) + val reg_fromhost = Reg(init=Bits(0, conf.xprlen)) val reg_coreid = Reg(Bits(width = 16)) val reg_k0 = Reg(Bits(width = conf.xprlen)) val reg_k1 = Reg(Bits(width = conf.xprlen)) val reg_ptbr = Reg(UInt(width = PADDR_BITS)) - val reg_vecbank = RegReset(SInt(-1,8).toBits) - val reg_stats = RegReset(Bool(false)) - val reg_error_mode = RegReset(Bool(false)) + val reg_vecbank = Reg(init=SInt(-1,8).toBits) + val reg_stats = Reg(init=Bool(false)) + val reg_error_mode = Reg(init=Bool(false)) val reg_status = Reg(new Status) // reset down below - val r_irq_timer = RegReset(Bool(false)) - val r_irq_ipi = RegReset(Bool(true)) + val r_irq_timer = Reg(init=Bool(false)) + val r_irq_ipi = Reg(init=Bool(true)) val host_pcr_req_valid = Reg(Bool()) // don't reset val host_pcr_req_fire = host_pcr_req_valid && io.rw.cmd === PCR.N diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala index 01449e53..a49cd2be 100644 --- a/rocket/src/main/scala/dpath_vec.scala +++ b/rocket/src/main/scala/dpath_vec.scala @@ -110,8 +110,8 @@ class rocketDpathVec extends Module val max_threads = UInt(WIDTH_BMASK) val uts_per_bank = Mux(Bool(HAVE_PVFB) & nreg_mod_bank > max_threads, max_threads, nreg_mod_bank) - val reg_hwvl = RegReset(UInt(32, 12)) - val reg_appvl0 = RegReset(Bool(true)) + val reg_hwvl = Reg(init=UInt(32, 12)) + val reg_appvl0 = Reg(init=Bool(true)) val hwvl_vcfg = (uts_per_bank * io.vecbankcnt)(11,0) val hwvl = @@ -123,9 +123,9 @@ class rocketDpathVec extends Module Mux(io.wdata(11,0) < hwvl, io.wdata(11,0).toUInt, hwvl.toUInt)) - val reg_nxregs = RegReset(UInt(32, 6)) - val reg_nfregs = RegReset(UInt(32, 6)) - val reg_appvl = RegReset(UInt(0, 12)) + val reg_nxregs = Reg(init=UInt(32, 6)) + val reg_nfregs = Reg(init=UInt(32, 6)) + val reg_appvl = Reg(init=UInt(0, 12)) when (io.valid) { diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index ac5f80e6..c6803a67 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -198,7 +198,7 @@ class FPToInt extends Module } val in = Reg(new Input) - val valid = RegUpdate(io.in.valid) + val valid = Reg(next=io.in.valid) when (io.in.valid) { def upconvert(x: UInt) = hardfloat.recodedFloatNToRecodedFloatM(x, Bits(0), 23, 9, 52, 12)._1 when (io.in.bits.cmd === FCMD_STORE) { @@ -381,7 +381,7 @@ class FPUSFMAPipe(val latency: Int) extends Module val one = Bits("h80000000") val zero = Cat(io.in1(32) ^ io.in2(32), Bits(0, 32)) - val valid = RegUpdate(io.valid) + val valid = Reg(next=io.valid) when (io.valid) { cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0)) rm := io.rm @@ -418,7 +418,7 @@ class FPUDFMAPipe(val latency: Int) extends Module val one = Bits("h8000000000000000") val zero = Cat(io.in1(64) ^ io.in2(64), Bits(0, 64)) - val valid = RegUpdate(io.valid) + val valid = Reg(next=io.valid) when (io.valid) { cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0)) rm := io.rm @@ -451,10 +451,10 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module when (io.ctrl.valid) { ex_reg_inst := io.dpath.inst } - val ex_reg_valid = Reg(updateData=io.ctrl.valid, resetData=Bool(false)) - val mem_reg_valid = Reg(updateData=ex_reg_valid && !io.ctrl.killx, resetData=Bool(false)) + val ex_reg_valid = Reg(next=io.ctrl.valid, init=Bool(false)) + val mem_reg_valid = Reg(next=ex_reg_valid && !io.ctrl.killx, init=Bool(false)) val killm = io.ctrl.killm || io.ctrl.nack_mem - val wb_reg_valid = Reg(updateData=mem_reg_valid && !killm, resetData=Bool(false)) + val wb_reg_valid = Reg(next=mem_reg_valid && !killm, init=Bool(false)) val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.dpath.inst @@ -464,7 +464,7 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // load response - val load_wb = RegUpdate(io.dpath.dmem_resp_val) + val load_wb = Reg(next=io.dpath.dmem_resp_val) val load_wb_single = RegEnable(io.dpath.dmem_resp_type === MT_W || io.dpath.dmem_resp_type === MT_WU, io.dpath.dmem_resp_val) val load_wb_data = RegEnable(io.dpath.dmem_resp_data, io.dpath.dmem_resp_val) val load_wb_tag = RegEnable(io.dpath.dmem_resp_tag, io.dpath.dmem_resp_val) @@ -546,7 +546,7 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) - val wen = RegReset(Bits(0, maxLatency-1)) + val wen = Reg(init=Bits(0, maxLatency-1)) val winfo = Vec.fill(maxLatency-1){Reg(Bits())} val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint) val (write_port_busy, mem_winfo) = (Reg(Bool()), Reg(Bits())) @@ -592,11 +592,11 @@ class FPU(sfma_latency: Int, dfma_latency: Int) extends Module val fp_inflight = wb_reg_valid && wb_ctrl.toint || wen.orR val fsr_busy = mem_ctrl.rdfsr && fp_inflight || wb_reg_valid && wb_ctrl.wrfsr - val units_busy = mem_reg_valid && mem_ctrl.fma && RegUpdate(Mux(ctrl.single, io.sfma.valid, io.dfma.valid)) + val units_busy = mem_reg_valid && mem_ctrl.fma && Reg(next=Mux(ctrl.single, io.sfma.valid, io.dfma.valid)) io.ctrl.nack_mem := fsr_busy || units_busy || write_port_busy io.ctrl.dec <> fp_decoder.io.sigs def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(Bool(false))(_||_) - io.ctrl.sboard_set := wb_reg_valid && RegUpdate(useScoreboard(_._1.cond(mem_ctrl))) + io.ctrl.sboard_set := wb_reg_valid && Reg(next=useScoreboard(_._1.cond(mem_ctrl))) io.ctrl.sboard_clr := wen(0) && useScoreboard(x => wsrc === UInt(x._2)) io.ctrl.sboard_clra := waddr // we don't currently support round-max-magnitude (rm=4) diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index eb4f536a..f327dddd 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -60,7 +60,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi require(short_request_bits % w == 0) val rx_count_w = 13 + log2Up(64) - log2Up(w) // data size field is 12 bits - val rx_count = RegReset(UInt(0,rx_count_w)) + val rx_count = Reg(init=UInt(0,rx_count_w)) val rx_shifter = Reg(Bits(width = short_request_bits)) val rx_shifter_in = Cat(io.host.in.bits, rx_shifter(short_request_bits-1,w)) val next_cmd = rx_shifter_in(3,0) @@ -100,7 +100,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi Mux(cmd === cmd_readcr || cmd === cmd_writecr, size != UInt(1), Bool(true))) - val tx_count = RegReset(UInt(0, rx_count_w)) + val tx_count = Reg(init=UInt(0, rx_count_w)) val tx_subword_count = tx_count(log2Up(short_request_bits/w)-1,0) val tx_word_count = tx_count(rx_count_w-1, log2Up(short_request_bits/w)) val packet_ram_raddr = tx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1) @@ -112,7 +112,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr || cmd === cmd_writecr), size, UInt(0)) val tx_done = io.host.out.ready && tx_subword_count.andR && (tx_word_count === tx_size || tx_word_count > UInt(0) && packet_ram_raddr.andR) - val mem_acked = RegReset(Bool(false)) + val mem_acked = Reg(init=Bool(false)) val mem_gxid = Reg(Bits()) val mem_gsrc = Reg(UInt(width = conf.ln.idBits)) val mem_needs_ack = Reg(Bool()) @@ -125,7 +125,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi io.mem.grant.ready := Bool(true) val state_rx :: state_pcr_req :: state_pcr_resp :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(9) { UInt() } - val state = RegReset(state_rx) + val state = Reg(init=state_rx) val rx_cmd = Mux(rx_word_count === UInt(0), next_cmd, cmd) when (state === state_rx && rx_done) { @@ -134,7 +134,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi state_tx)) } - val mem_cnt = RegReset(UInt(0, log2Up(REFILL_CYCLES))) + val mem_cnt = Reg(init=UInt(0, log2Up(REFILL_CYCLES))) val x_init = Module(new Queue(new Acquire, 1)) when (state === state_mem_req && x_init.io.enq.ready) { state := Mux(cmd === cmd_writemem, state_mem_wdata, state_mem_rdata) @@ -198,8 +198,8 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi val pcrReadData = Reg(Bits(width = io.cpu(0).pcr_rep.bits.getWidth)) for (i <- 0 until nTiles) { - val my_reset = RegReset(Bool(true)) - val my_ipi = RegReset(Bool(false)) + val my_reset = Reg(init=Bool(true)) + val my_ipi = Reg(init=Bool(false)) val cpu = io.cpu(i) val me = pcr_coreid === UInt(i) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 262f3841..bae95113 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -61,10 +61,10 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu val s1_pc = Reg(UInt()) val s1_same_block = Reg(Bool()) - val s2_valid = RegReset(Bool(true)) - val s2_pc = RegReset(UInt(START_ADDR)) - val s2_btb_hit = RegReset(Bool(false)) - val s2_xcpt_if = RegReset(Bool(false)) + val s2_valid = Reg(init=Bool(true)) + val s2_pc = Reg(init=UInt(START_ADDR)) + val s2_btb_hit = Reg(init=Bool(false)) + val s2_xcpt_if = Reg(init=Bool(false)) val btbTarget = Cat(btb.io.target(VADDR_BITS-1), btb.io.target) val pcp4_0 = s1_pc + UInt(c.ibytes) @@ -144,16 +144,16 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module } val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(4) { UInt() } - val state = RegReset(s_ready) + val state = Reg(init=s_ready) val invalidated = Reg(Bool()) val stall = !io.resp.ready val rdy = Bool() - val s2_valid = RegReset(Bool(false)) + val s2_valid = Reg(init=Bool(false)) val s2_addr = Reg(UInt(width = PADDR_BITS)) val s2_any_tag_hit = Bool() - val s1_valid = RegReset(Bool(false)) + val s1_valid = Reg(init=Bool(false)) val s1_pgoff = Reg(UInt(width = PGIDX_BITS)) val s1_addr = Cat(io.req.bits.ppn, s1_pgoff).toUInt val s1_tag = s1_addr(c.tagbits+c.untagbits-1,c.untagbits) @@ -195,7 +195,7 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module tag_raddr := s0_pgoff(c.untagbits-1,c.offbits) } - val vb_array = RegReset(Bits(0, c.lines)) + val vb_array = Reg(init=Bits(0, c.lines)) when (refill_done && !invalidated) { vb_array := vb_array.bitSet(Cat(repl_way, s2_idx), Bool(true)) } diff --git a/rocket/src/main/scala/multiplier.scala b/rocket/src/main/scala/multiplier.scala index 7d329de7..95d1218b 100644 --- a/rocket/src/main/scala/multiplier.scala +++ b/rocket/src/main/scala/multiplier.scala @@ -33,7 +33,7 @@ class Multiplier(unroll: Int = 1, earlyOut: Boolean = false)(implicit conf: Rock val w = (w0+1+unroll-1)/unroll*unroll val cycles = w/unroll - val r_val = RegReset(Bool(false)) + val r_val = Reg(init=Bool(false)) val r_prod = Reg(Bits(width = w*2)) val r_lsb = Reg(Bits()) val r_cnt = Reg(UInt(width = log2Up(cycles+1))) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 87c35d95..5e8b4c96 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -189,7 +189,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte } val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) { UInt() } - val state = RegReset(s_invalid) + val state = Reg(init=s_invalid) val acquire_type = Reg(UInt()) val release_type = Reg(UInt()) @@ -280,7 +280,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte io.req_pri_rdy := state === s_invalid io.req_sec_rdy := sec_rdy && rpq.io.enq.ready - val meta_hazard = RegReset(UInt(0,2)) + val meta_hazard = Reg(init=UInt(0,2)) when (meta_hazard != 0) { meta_hazard := meta_hazard + 1 } when (io.meta_write.fire()) { meta_hazard := 1 } io.probe_rdy := !idx_match || (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && meta_hazard === 0) @@ -338,7 +338,7 @@ class MSHRFile(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends M val fence_rdy = Bool(OUTPUT) } - val sdq_val = RegReset(Bits(0, conf.nsdq)) + val sdq_val = Reg(init=Bits(0, conf.nsdq)) val sdq_alloc_id = PriorityEncoder(~sdq_val(conf.nsdq-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = io.req.valid && io.req.ready && isWrite(io.req.bits.cmd) @@ -432,9 +432,9 @@ class WritebackUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte val release_data = Decoupled(new ReleaseData) } - val valid = RegReset(Bool(false)) - val r1_data_req_fired = RegReset(Bool(false)) - val r2_data_req_fired = RegReset(Bool(false)) + val valid = Reg(init=Bool(false)) + val r1_data_req_fired = Reg(init=Bool(false)) + val r2_data_req_fired = Reg(init=Bool(false)) val cmd_sent = Reg(Bool()) val cnt = Reg(UInt(width = log2Up(REFILL_CYCLES+1))) val req = Reg(new WritebackReq) @@ -506,7 +506,7 @@ class ProbeUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends } val s_reset :: s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: Nil = Enum(9) { UInt() } - val state = RegReset(s_invalid) + val state = Reg(init=s_invalid) val line_state = Reg(UInt()) val way_en = Reg(Bits()) val req = Reg(new InternalProbe) @@ -575,7 +575,7 @@ class MetaDataArray(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte val resp = Vec.fill(conf.ways){(new MetaData).asOutput} } - val rst_cnt = RegReset(UInt(0, log2Up(conf.sets+1))) + val rst_cnt = Reg(init=UInt(0, log2Up(conf.sets+1))) val rst = rst_cnt < conf.sets when (rst) { rst_cnt := rst_cnt+1 } @@ -743,19 +743,19 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends val mshrs = Module(new MSHRFile) io.cpu.req.ready := Bool(true) - val s1_valid = Reg(updateData=io.cpu.req.fire(), resetData=Bool(false)) + val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false)) val s1_req = Reg(io.cpu.req.bits.clone) val s1_valid_masked = s1_valid && !io.cpu.req.bits.kill - val s1_replay = RegReset(Bool(false)) + val s1_replay = Reg(init=Bool(false)) val s1_clk_en = Reg(Bool()) - val s2_valid = Reg(updateData=s1_valid_masked, resetData=Bool(false)) + val s2_valid = Reg(next=s1_valid_masked, init=Bool(false)) val s2_req = Reg(io.cpu.req.bits.clone) - val s2_replay = Reg(updateData=s1_replay, resetData=Bool(false)) + val s2_replay = Reg(next=s1_replay, init=Bool(false)) val s2_recycle = Bool() val s2_valid_masked = Bool() - val s3_valid = RegReset(Bool(false)) + val s3_valid = Reg(init=Bool(false)) val s3_req = Reg(io.cpu.req.bits.clone) val s3_way = Reg(Bits()) @@ -865,7 +865,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends val s2_hit = s2_tag_match && tl.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === tl.co.newStateOnHit(s2_req.cmd, s2_hit_state) // load-reserved/store-conditional - val lrsc_count = RegReset(UInt(0)) + val lrsc_count = Reg(init=UInt(0)) val lrsc_valid = lrsc_count.orR val lrsc_addr = Reg(UInt()) val (s2_lr, s2_sc) = (s2_req.cmd === M_XLR, s2_req.cmd === M_XSC) @@ -980,7 +980,7 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release.data // store->load bypassing - val s4_valid = Reg(updateData=s3_valid, resetData=Bool(false)) + val s4_valid = Reg(next=s3_valid, init=Bool(false)) val s4_req = RegEnable(s3_req, s3_valid && metaReadArb.io.out.valid) val bypasses = List( ((s2_valid_masked || s2_replay) && !s2_sc_fail, s2_req, amoalu.io.out), @@ -1018,14 +1018,14 @@ class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends s2_valid_masked := s2_valid && !s2_nack val s2_recycle_ecc = (s2_valid || s2_replay) && s2_hit && s2_data_correctable - val s2_recycle_next = RegReset(Bool(false)) + val s2_recycle_next = Reg(init=Bool(false)) when (s1_valid || s1_replay) { s2_recycle_next := (s1_valid || s1_replay) && s2_recycle_ecc } s2_recycle := s2_recycle_ecc || s2_recycle_next // after a nack, block until nack condition resolves to save energy - val block_fence = RegReset(Bool(false)) + val block_fence = Reg(init=Bool(false)) block_fence := (s2_valid && s2_req.cmd === M_FENCE || block_fence) && !mshrs.io.fence_rdy - val block_miss = RegReset(Bool(false)) + val block_miss = Reg(init=Bool(false)) block_miss := (s2_valid || block_miss) && s2_nack_miss when (block_fence || block_miss) { io.cpu.req.ready := Bool(false) diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index 806ac261..3681586c 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -40,7 +40,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module require(VPN_BITS == levels * bitsPerLevel) val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(5) { UInt() }; - val state = RegReset(s_ready) + val state = Reg(init=s_ready) val count = Reg(UInt(width = log2Up(levels))) val r_req_vpn = Reg(Bits()) diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala index 99997b39..1c3af620 100644 --- a/rocket/src/main/scala/tlb.scala +++ b/rocket/src/main/scala/tlb.scala @@ -22,7 +22,7 @@ class RocketCAM(entries: Int, tag_bits: Int) extends Module { val io = new CAMIO(entries, addr_bits, tag_bits); val cam_tags = Vec.fill(entries){Reg(Bits(width = tag_bits))} - val vb_array = RegReset(Bits(0, entries)) + val vb_array = Reg(init=Bits(0, entries)) when (io.write) { vb_array := vb_array.bitSet(io.write_addr, Bool(true)); cam_tags(io.write_addr) := io.write_tag @@ -94,7 +94,7 @@ class TLB(entries: Int) extends Module } val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) { UInt() } - val state = RegReset(s_ready) + val state = Reg(init=s_ready) val r_refill_tag = Reg(UInt()) val r_refill_waddr = Reg(UInt()) diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index b656d16e..ed008423 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -117,12 +117,12 @@ case class WideCounter(width: Int, inc: Bool = Bool(true)) { private val isWide = width >= 4 private val smallWidth = if (isWide) log2Up(width) else width - private val small = RegReset(UInt(0, smallWidth)) + private val small = Reg(init=UInt(0, smallWidth)) private val nextSmall = small + UInt(1, smallWidth+1) when (inc) { small := nextSmall(smallWidth-1,0) } private val large = if (isWide) { - val r = RegReset(UInt(0, width - smallWidth)) + val r = Reg(init=UInt(0, width - smallWidth)) when (inc && nextSmall(smallWidth)) { r := r + UInt(1) } r } else null