riscv/rocket-chip
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final Reg changes

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This commit is contained in:
Henry Cook
2013-08-15 15:28:15 -07:00
parent b570435847
commit 3a266cbbfa
16 changed files with 117 additions and 117 deletions
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rocket/src/main/scala/ptw.scala
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@ -40,7 +40,7 @@ class PTW(n: Int)(implicit conf: RocketConfiguration) extends Module
require(VPN_BITS == levels * bitsPerLevel)
val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(5) { UInt() };
val state = RegReset(s_ready)
val state = Reg(init=s_ready)
val count = Reg(UInt(width = log2Up(levels)))
val r_req_vpn = Reg(Bits())